SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The configuration registers are accessed through the OCP2SCP3 L4 adapter register space using the SCP interface of the DPLLCTRL_SATA. This includes all the configuration signals and returning status signals.
All writes must be 32-bit operations, because the SCP interface always transfers 32 bits; 16- or 8-bit operations may lead to unpredictable errors.
Because the SATA_PHY directly provides parallel data interface clocks RX_CLK and TX_CLK to the SATA controller, the DPLLCTRL_SATA and DPLL_SATA must be configured before any data transfer between the SATA controller and an external SATA storage device.