SPRUI04F july 2015 – april 2023
Without the .mptr directives in Example5-10, the loads of a[0-1] and b[0-1] are scheduled in parallel, and the loads of a[2-3] and b[2-3] might be scheduled in parallel. This results in a 50% chance that a memory conflict will occur on every cycle. However, the loop kernel shown in Example5-11 can never have a memory bank conflict.
In Example5-8, if .mptr directives had been used to specify that a and b point to different bases, then the assembly optimizer would never find a schedule for a 1-cycle loop kernel, because there would always be a memory bank conflict. However, it would find a schedule for a 2-cycle loop kernel.