SPRUIC4D January   2017  – June 2022

 

  1.   Piccolo F280049C controlCARD Information Guide
  2. 1Introduction
  3. 2Errata
    1. 2.1 Warnings, Notes, and Errata
  4. 3Getting Familiar With the controlCARD
    1. 3.1 F280049C controlCARD Features
    2. 3.2 F28004x Device Description
    3. 3.3 Assumed Operating Conditions
    4. 3.4 Using the controlCARD
    5. 3.5 Software Development
  5. 4Special Notes
    1. 4.1 XDS100v2 Emulator and SCI/UART Connectivity
    2. 4.2 cJTAG Usage
    3. 4.3 Evaluation of the Programmable Gain Amplifier (PGA)
    4. 4.4 Evaluation of the Analog-to-Digital Converters (ADCs)
    5. 4.5 Evaluation of the Internal DC/DC Converter
  6. 5Hardware References
  7. 6Revision History

5 Hardware References

Table 5-1 shows the various connections available on the board. Figure 5-1 illustrates the location of many of these components on the board.

WARNING:

When the controlCARD is used in a high-voltage setup, it is the user’s responsibility to confirm that the voltages and isolation requirements are identified and understood prior to energizing the board or simulation. When energized, the controlCARD or components connected to the controlCARD should not be touched. Furthermore, the capacitor C26:A should be removed to minimize the possibility of leakage current flowing across the isolation barrier of the controlCARD.

GUID-D618BB14-37CE-4BB2-B2B8-C0C484F481EC-low.pngFigure 5-1 Key Components on the controlCARD
Table 5-1 Hardware References
Connectors
J1:AEmulation/UART connector - USB mini A connector used to provide XDS100v2 emulation and USB-to-UART(SCI) communication through FTDI logic. S1:A determines which connections are enabled to the MCU.
Jumpers
J1FSI Connector - Gives an ability to connect FSI signals from the F280049C to another board.
LEDs
D1Turns on when the controlCARD is powered ON (green)
D2Controlled by GPIO-31 with negative logic (red)
D3Controlled by GPIO-34 with negative logic (red)
D2:ATurns on when ISO JTAG logic is powered on (green)
D3:AJTAG/UART RX toggle indicator (blue)
D4:AJTAG/UART TX toggle indicator (blue)
Resistors and Capacitors (default setting in BOLD)
R18, R19, R21, R22GPIO22/23 configuration resistors
These resistors allow the user to choose whether GPIO22/23 is used as GPIO (and go to the baseboard) or whether they will be used in conjunction with the F280049C MCU’s internal DC/DC capability:
  • R18,R19 populated with 0-Ω resistors and R21,R22 unpopulated – GPIO22 and GPIO23 are used as GPIO and go to the baseboard through EC1. The internal DC/DC cannot be used.
  • R18,R19 unpopulated and R21,R22 populated with 0-Ω resistors – Internal DC/DC can be used to generate the 1.2-V VDD power rail. GPIO22 and GPIO23 are used as VFBSW and VSW, respectively. The internal DC/DC can be used.
C19, C20, C21These capacitors should be populated when the F280049C’s internal DC/DC capability is used. C19 should be populated with a 2.2-µF capacitor. C20 and C21 should each be populated with a 10-µF capacitor.
R24, C28R24 and C28 create an optional snubber circuit, which can be used if the DC/DC is used.
R36-R47,R49,R53, R60-R64, C41-C47, and C48-C59Optional RC input filter for all ADC/PGA inputs
C34-C40PGA filter capacitor when PGA filtering is used
R55-R59PGA-GND configuration resistors
R48,R50-R52,R54These resistors control whether the negative input (PGAGND) for each PGA are grounded locally or whether they should be grounded through pins on the HSEC connector (for use in Kelvin grounding).
By default, resistors R55-R59 are not populated and R48, R50-R52, R54 are populated. Because of this, all the PGAs are, by default, expected to be referenced to ground by the baseboard. If, for example, R55 was populated and R48 was unpopulated, then PGA1’s PGAGND would be grounded on the controlCARD.
Switches (default position in BOLD)
S1
(Installed with 180 degree rotation)		Boot Mode Selection Switch
See Table 5-2 for a list of selectable boot modes. See the device datasheet and TRM for more information about device boot behavior.
Left (Switch 2) – GPIO24 Configuration Switch:
  • In the up position – GPIO24 is pulled high
  • In the down position – GPIO24 is pulled low

Right (Switch 1) – GPIO32 Configuration Switch:
  • In the up position – GPIO32 is pulled high
  • In the down position – GPIO32 is pulled low
S2GPIO10/GPIO35 Configuration Switches
  • In the up position – GPIO10 goes to pin 60 of the HSEC connector. If S4’s switch 1 is in the up position, GPIO35 goes to pin 85 of the HSEC connector.
  • In the down position – GPIO10 goes to pin 85 of the HSEC connector. If S4’s switch 1 is in the up position, GPIO35 goes to pin 60 of the HSEC connector.
S3
(Installed with 180 degree rotation)		GPIO08/GPIO37 Configuration Switches
  • In the up position – GPIO08 goes to pin 87 of the HSEC connector. If S4’s switch 2 is in the up position, GPIO37 goes to pin 58 of the HSEC connector.
  • In the down position – GPIO08 goes to pin 58 of the HSEC connector. If S4’s switch 2 is in the up position, GPIO37 goes to pin 87 of the HSEC connector.
S4JTAG/cJTAG Selection Switch
  • In the up position – 2-pin cJTAG mode is expected to be used. GPIO35 and GPIO37 go to the baseboard based on the settings of S2 and S3, respectively.
  • In the down position – 4-pin standard JTAG is expected to be used. GPIO35 and GPIO37 are used to support JTAG functionality. The on-card XDS100v2 emulator requires 4-pin JTAG to be used.
S5
(Installed with 180 degree rotation)		GPIO24/GPIO25 Configuration Switches
Left (Switch 2) – GPIO25 Configuration Switch:
  • In the up position – GPIO25 goes to pin 77 of the HSEC connector.
  • In the down position – GPIO25 goes to pin 102 of the HSEC connector.

Right (Switch 1) – GPIO24 Configuration Switch:
  • In the up position – GPIO24 goes to pin 75 of the HSEC connector.
  • In the down position – GPIO24 goes to pin 100 of the HSEC connector.
S6GPIO26/GPIO27 Configuration Switches
Left (Switch 1) – GPIO26 Configuration Switch:
  • In the up position – GPIO26 goes to pin 107 of the HSEC connector.
  • In the down position – GPIO26 goes to pin 79 of the HSEC connector.

Right (Switch 2) – GPIO27 Configuration Switch:
  • In the up position – GPIO27 goes to pin 109 of the HSEC connector.
  • In the down position – GPIO27 goes to pin 81 of the HSEC connector.
S7PGA Filter Configuration Switches
From the left, the switches control whether PGA1-PGA7’s outputs, respectively, are filtered. The eighth switch of S7 is not used.
Each switch:
  • In the up position – an HSEC pin is connected to the respective PGA+ input pin, and is now also tied to an additional ADC input pin. In software, PGA output filtering, for the respective PGA, functionality should NOT be used.
  • In the down position – an HSEC pin only goes to the PGA+ input pin. PGA output filtering, for the respective PGA, may be used.

The up position for S7’s switch 6 (PGA6) is implemented differently from the other PGAs. PGA6_OF may be accessed through the HSEC connector independently of PGA6_IN, whereas the other PGAs will have their respective PGAn_OF and PGAn_IN signals shorted together.
S8
(Installed with 90 degree rotation)		ADC VREFHI Control Switch for ADC modules
Top (Switch 1) – VREFHI Control Switch for ADC module A:
  • In the left position – ADC-A should be configured to use the internal voltage reference.
  • In the right position – ADC-A is configured to use an external voltage reference, which should be connected to pin 45 of the HSEC connector.

Bottom (Switch 2) – VREFHI Control Switch for ADC module B and module C:
  • In the left position – ADC-B and ADC-C should be configured to use the internal voltage reference.
  • In the right position – ADC-B and ADC-C are configured to use an external voltage reference, which should be connected to pin 45 of the HSEC connector.
S1:AIsolated emulation and UART communication enable switches
Left (Switch 1) – JTAG Enable:
  • Up (on) – All signals between the XDS100v2 emulation logic and the MCU are connected. This setting is valid when the MCU is being debugged or programmed through the on-card XDS100v2 emulator.
  • Down (off) – The XDS100v2 emulation logic will NOT be connected to the MCU. This setting is valid when the device boots from FLASH, boots from a peripheral directly, or when an external JTAG emulator is used.

Right (Switch 2) – ISO UART communication enable:
  • Up (on) – The C2000 MCU’s GPIO-28 (and pin76 of the 180pin controlCARD connector) are coupled to the FTDI’s USB-to-Serial adapter. This allows UART communication to a computer through the FTDI chip. However, in this position, GPIO-28 is forced high by the FTDI chip. Functionality of pin76 on the connector is limited.
  • Down (off) – The C2000 MCU will NOT be connected to the FTDI USB-to-Serial adapter. Pin76 of the 180pin controlCARD connector is directly connected to GPIO-28.
Table 5-2 Boot Mode Switch (S1) Positions
Mode # GPIO-24 (Left, Switch 2) GPIO-32 (Right, Switch 1) Boot from
000 (Down)0 (Down)Parallel I/O
010 (Down)1 (Up)Boot from SCI / Wait Mode
021 (Up)0 (Down)Boot from CAN
031 (Up)1 (Up)Boot from FLASH