SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Figure 12-1163 depicts a simplified internal block diagram of the CSI_TX_IF and its surroundings.
The CSI2 core streams 4 channels of data to the several export paths.
Stream0 goes through the PSI_L that converts 128(4x32) bits pixel data and converts it to single 32-bit CSI streaming protocol of pixel data. Each 128 bit set of PSI_L data is split into N M-bit data transfers based on the SIZE_CFG bitfield setting in the CSI_TX_IF_DMACNTX_j register for a given thread. See memory organization details in . Via register mapping in the CSI_TX_IF_DMACNTX_j register the PSIL thread ID is mapped to a virtual channel and a data type. The CSI_TX_IF_DMACNTX_j register is the thread filter. There are 32 dma context registers. Figure 12-1164 shows the stream to PSI_L thread mapping.
Software must take the following notes in consideration
Registers CSI_TX_IF_L2L_DELAY_j control the line start to next line start. Also register CSI_TX_IF_F2F_DELAY_y control the last line of frame to next start of frame first line start of next frame. Buffering of PSI_L data is 2k×128 RAM.
Stream1 streams data from the Color Bar generator. It supports YUV422 8bit format only. CSI_TX_IF_COLOR_PARAM register is used to control height and width information. Width is divided by 8 for each color section. Colors are defined below. Transfers are done on the Stream1 interface in 32-bit packed 8-bit pixel format(required programming in CSI_TX_IF core). Virtual channel and data type is configurable in CSI_TX_IF_COLOR_CNTL register. Data selection inside CSI_TX_IF controller maps data type information. CSI_TX_IF_COLOR_START_DELAY register can configure delays from enabled to start. CSI_TX_IF_COLOR_LINE_DELAY, and CSI_TX_IF_COLOR_FRAME_DELAY register can delay last line to first line of new frame. Once enabled, it will continuously send out frames until disabled. Once disabled, it will stop at end of current frame. Table 12-1539 shows the Color Bar format.
Color | Y | CB | CR |
---|---|---|---|
White | 235 | 128 | 128 |
Yellow | 162 | 44 | 142 |
Cyan | 131 | 156 | 44 |
Green | 112 | 72 | 58 |
Magenta | 84 | 184 | 198 |
Red | 65 | 100 | 212 |
Blue | 35 | 212 | 114 |
Black | 16 | 128 | 128 |
Stream2 and Stream3 stream data via a loopback path from the CSI_RX_IF.
Program limitations apply on the CSI_RX_IF and CSI_TX_IF sides. The CSI_TX_IF only supports single, non interleaved virtual channels. Program restriction on CSI_RX_IF side must limit this.
The CSI_TX_IF will use Stream2 and Stream3 to support 2 virtual channels of CSI_RX_IF data. The CSI_RX_IF can stream interleaved virtual channels of data. It is limited to programming the CSI_RX_IF so that it only sends data on up to 2 static virtual channels. The VC0 and VC1 fields in CSI_TX_IF_RETRANS_CNTL register need to be programmed to match which virtual channels are streamed on the CSI_RX_IF side so that the CSI_TX_IF can stream them. CSI_TX_IF can only stream a single virtual channel at any given time. Only RAW data formats can be used for this retransmit interface due to CSI_TX_IF limitations.
It is a requirement that only PSI_L/DMA, color bar, or loopback streams are not active at the same point in time. The intended use model is not to have multiple combinations active at any given time. The main issue with this is that RAMs are not sized for concurrent operation and will likely overflow resulting in data loss. The 2 loopback streams can be active at the same time just not in addition to the color or DMA streams.