SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
A single DRU module is integrated in the device MAIN domain. Figure 10-40 shows the integration of DRU.
Table 10-212 through Table 10-214 summarize the integration of DRU in device MAIN domain.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
DRU | PSC0 | PD0 | LPSC0 | CBASS0 (Accessed through NAVSS0 and then through MSMC) | |
PSI-L |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
DRU | DRU_CLK | MAIN_SYSCLK0 | PLLCTRL0 | DRU clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
DRU | DRU_RST | MOD_G_RST | LPSC0 | DRU reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
DRU | DRU_PROTOCOL_ERROR | CLEC_INTR_IN_17 | CLEC | DRU protocol violation event | Level |
DRU_COMPLETE_EVENT[31-0] | CLEC_INTR_IN_[95-64] | CLEC | DRU completion events | Level | |
DRU_ERROR_EVENT[31-0] | CLEC_INTR_IN_[159-128] | CLEC | DRU error completion events | Level | |
DRU_LOCALOUT_EVENT[31-0] | CLEC_INTR_IN_[223-192] | CLEC | DRU local output events | Level | |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
DRU | - | - | - | - | - |
For more information on the DRU events, see Section 10.4.3.2.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.