SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
VPFE_PCR and VPFE_SDR_ADDR registers are latched by the CCDC_VD signal if the VPFE_CCDCFG[15] VDLC is 0 (see VPFE CCDC_VD Latched Registers for more information). This important feature provides a reliable way to enable/disable the VPFE module and/or modify the memory pointers in-between frames. For example, the VPFE interrupt service routine can program the VPFE_SDR_ADDR register to a new value before the end of the current frame. By doing so, the current frame is received without any interruption and the new external memory address (VPFE_SDR_ADDR register) is used for receiving the next frame.