The VPFE module supports the following features:
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- Encompasses a buffer memory for interfacing to the DMA at the chip level and preventing the charge-coupled device (CCD) Controller from overflowing.
- Support for conventional Bayer pattern and Foveon sensor formats.
- Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator
- Support for progressive (non-interlaced) and interlaced sensors (hardware support for up to 2 fields and firmware support for higher number of fields, typically 3-, 4-, and 5-field sensors).
- Support for up to 110-MHz sensor clock.
- Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8- or 16-bit).
- Support for YCbCr 422 format, either 8- or 16-bit with discrete HSYNC and VSYNC signals.
- Support for up to 16-bit input.
- Generates optical black clamping signals.
- Support for digital clamping and black level compensation.
- Support for 10-bit to 8-bit A-law compression.
- Support for a low-pass filter prior to writing to DDR. If this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output.
- Support for generating output to range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area).
- Support for downsampling via programmable culling patterns.
- Ability to control output to the DDR via an external write enable signal.
- Support for up to 16K pixels (image size) in both the horizontal and vertical directions.
- Region-based Address Translation (RAT) module for converting legacy 32-bit to 48-bit addressing scheme in the write DMA path.