Integrated in MAIN domain are two instances of C66x DSP based on the TI's standard TMS320C66x DSP CorePac module. Each C66x DSP supports the following main features:
- Fixed/Floating-point C66x CPU based on a superset of the C64x+ and C67x+ ISA
- Program memory controller (PMC) with 32KB L1 program memory (L1P), configurable as cache and/or SRAM
- Data memory controller (DMC) with 32KB L1 data memory (L1D), configurable as cache and/or SRAM
- Unified memory controller (UMC) with 288KB L2 memory, only part of which is cacheable
- Internal DMA (IDMA) engine
- External memory controller (EMC)
- Extended memory controller (XMC)
- Address extension/translation (32-bit to 48-bit)
- Memory protection for multiple segments and all internal L1/L2 RAMs
- Error detection and correction
- Integrated C66x CorePac interrupt controller (INTC)
- Debug/emulation capabilities
Note: The C66x L1P memory is disabled (not supported) in this device.