SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Refresh commands are important memory operations to preserve memory contents, but they are also disruptive to system transaction flow. To minimize the impact, the DDR controller implements refresh on a per-bank basis. This does increase the quantity of refresh commands, but allows banks that are not targeted by the refresh to be accessed for read and write commands.
PBR is controlled through the following fields: