SPRUIL1D May   2019  – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Trademarks
    6.     Export Control Notice
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  C66x DSP Subsystem
      4. 1.3.4  C71x DSP Subsystem
      5. 1.3.5  Graphics Processing Unit
      6. 1.3.6  Multi-Standard HD Video Decoder
      7. 1.3.7  Multi-Standard HD Video Encoder
      8. 1.3.8  Vision Pre-processing Accelerator
      9. 1.3.9  Depth and Motion Perception Accelerator
      10. 1.3.10 Navigator Subsystem
      11. 1.3.11 Region-based Address Translation Module
      12. 1.3.12 Data Routing Unit
      13. 1.3.13 Display Subsystem
      14. 1.3.14 Camera Subsystem
      15. 1.3.15 Shared D-PHY Transmitter
      16. 1.3.16 Video Processing Front End
      17. 1.3.17 Multicore Shared Memory Controller
      18. 1.3.18 DDR Subsystem
      19. 1.3.19 Region-based Address Translation Module
      20. 1.3.20 General Purpose Input/Output Interface
      21. 1.3.21 Inter-Integrated Circuit Interface
      22. 1.3.22 Improved Inter-Integrated Circuit Interface
      23. 1.3.23 Multi-channel Serial Peripheral Interface
      24. 1.3.24 Universal Asynchronous Receiver/Transmitter
      25. 1.3.25 Gigabit Ethernet Switch
      26. 1.3.26 Peripheral Component Interconnect Express Subsystem
      27. 1.3.27 Universal Serial Bus (USB) Subsystem
      28. 1.3.28 SerDes
      29. 1.3.29 General Purpose Memory Controller with Error Location Module
      30. 1.3.30 Multimedia Card/Secure Digital Interface
      31. 1.3.31 Universal Flash Storage Interface
      32. 1.3.32 Enhanced Capture Module
      33. 1.3.33 Enhanced Pulse-Width Modulation Module
      34. 1.3.34 Enhanced Quadrature Encoder Pulse Module
      35. 1.3.35 Controller Area Network
      36. 1.3.36 Audio Tracking Logic
      37. 1.3.37 Multi-channel Audio Serial Port
      38. 1.3.38 Timers
      39. 1.3.39 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
            2. 3.3.4.2.3.2 Null Error Reporting
      5. 3.3.5 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.5.1 Overview and Feature List
          1. 3.3.5.1.1 Features Supported
          2. 3.3.5.1.2 Features Not Supported
        2. 3.3.5.2 Functional Description
          1. 3.3.5.2.1 Functional Operation
            1. 3.3.5.2.1.1  Overview
            2. 3.3.5.2.1.2  FIFOs
            3. 3.3.5.2.1.3  ID Allocator
            4. 3.3.5.2.1.4  Timer
            5. 3.3.5.2.1.5  Timeout Queue
            6. 3.3.5.2.1.6  Write Scoreboard
            7. 3.3.5.2.1.7  Read Scoreboard
            8. 3.3.5.2.1.8  Flush Mode
            9. 3.3.5.2.1.9  Flushing
            10. 3.3.5.2.1.10 Timeout Error Reporting
            11. 3.3.5.2.1.11 Command Timeout Error Reporting
            12. 3.3.5.2.1.12 Unexpected Response Reporting
            13. 3.3.5.2.1.13 Latency and Stalls
            14. 3.3.5.2.1.14 Bypass
            15. 3.3.5.2.1.15 Safety
        3. 3.3.5.3 Interrupt Conditions
          1. 3.3.5.3.1 Transaction Error Interrupt
            1. 3.3.5.3.1.1 Transaction Timeout
            2. 3.3.5.3.1.2 Unexpected Response
            3. 3.3.5.3.1.3 Command Timeout
        4. 3.3.5.4 Memory Map
          1. 3.3.5.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.5.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.5.4.3  Info Register (Base Address + 0x08)
          4. 3.3.5.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.5.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.5.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.5.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.5.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.5.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.5.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.5.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.5.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.5.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.5.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.5.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.5.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.5.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.5.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.5.5 Integration Overview
          1. 3.3.5.5.1 Parameterization Requirements
        6. 3.3.5.6 I/O Description
          1. 3.3.5.6.1 Clockstop Idle
          2. 3.3.5.6.2 Flush
          3. 3.3.5.6.3 Module I/O
        7. 3.3.5.7 User’s Guide
          1. 3.3.5.7.1 Programmer’s Guide
            1. 3.3.5.7.1.1 Initialization
            2. 3.3.5.7.1.2 Software Flush
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  OSPI Boot Device Configuration
      5. 4.3.5  xSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  I2C Boot Device Configuration
      9. 4.3.9  MMC/SD Card Boot Device Configuration
      10. 4.3.10 Ethernet Boot Device Configuration
      11. 4.3.11 USB Boot Device Configuration
      12. 4.3.12 PCIe Boot Device Configuration
      13. 4.3.13 UART Boot Device Configuration
      14. 4.3.14 GPMC NOR Boot Device Configuration
      15. 4.3.15 eMMC Boot Device Configuration
        1. 4.3.15.1 eMMC Flash
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 198
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI/xSPI Boot Parameter Table
      6. 4.4.6  GPMC NOR Boot Parameter Table
      7. 4.4.7  Ethernet Boot Parameter Table
      8. 4.4.8  USB Boot Parameter Table
      9. 4.4.9  MMCSD Boot Parameter Table
      10. 4.4.10 UART Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Generating X.509 Certificates
        1. 4.5.5.1 Key Generation
          1. 4.5.5.1.1 Degenerate RSA Keys
        2. 4.5.5.2 Configuration Script
      6. 4.5.6 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1  I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
          2. 4.6.1.2.2 Loading Image In Slave Mode
      2. 4.6.2  SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3  QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4  OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5  PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6  GPMC NOR Bootloader Operation
        1. 4.6.6.1 GPMC NOR Initialization Process
        2. 4.6.6.2 GPMC NOR Loading Process
      7. 4.6.7  Ethernet Bootloader Operation
        1. 4.6.7.1 Ethernet Initialization Process
        2. 4.6.7.2 Ethernet Loading Process
          1. 4.6.7.2.1 Ethernet Boot Data Formats
            1. 4.6.7.2.1.1 Limitations
            2. 4.6.7.2.1.2 BOOTP Request
              1. 4.6.7.2.1.2.1 MAC Header (DIX)
              2. 4.6.7.2.1.2.2 IPv4 Header
              3. 4.6.7.2.1.2.3 UDP Header
              4. 4.6.7.2.1.2.4 BOOTP Payload
              5. 4.6.7.2.1.2.5 TFTP
        3. 4.6.7.3 Ethernet Hand Over Process
      8. 4.6.8  USB Bootloader Operation
        1. 4.6.8.1 USB-Specific Attributes
          1. 4.6.8.1.1 DFU Device Mode
      9. 4.6.9  MMCSD Bootloader Operation
      10. 4.6.10 UART Bootloader Operation
        1. 4.6.10.1 Initialization Process
        2. 4.6.10.2 UART Loading Process
          1. 4.6.10.2.1 UART XMODEM
        3. 4.6.10.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  PRU_ICSSG Control Registers
            8. 5.1.3.3.1.8  Clock Muxing and Division Registers
            9. 5.1.3.3.1.9  Ethernet Port Operation Control Registers
            10. 5.1.3.3.1.10 PCIe Operation Control Registers
            11. 5.1.3.3.1.11 SERDES Lane Function Control Registers
            12. 5.1.3.3.1.12 DDRSS Dynamic Frequency Change Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Management Unit
          1. 5.2.2.1.1 Power OK (POK) Modules
            1. 5.2.2.1.1.1 POK Programming Model
          2. 5.2.2.1.2 Power on Reset (POR) Module
            1. 5.2.2.1.2.1 POR Overview
            2. 5.2.2.1.2.2 POR Integration
            3. 5.2.2.1.2.3 POR Functional Description
            4. 5.2.2.1.2.4 POR Programming Model
          3. 5.2.2.1.3 PoR/Reset Generator (PRG) Modules
            1. 5.2.2.1.3.1 PRG Overview
            2. 5.2.2.1.3.2 PRG Integration
            3. 5.2.2.1.3.3 PRG Programming Model
          4. 5.2.2.1.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.1.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.1.5.1 VTM Overview
              1. 5.2.2.1.5.1.1 VTM Features
              2. 5.2.2.1.5.1.2 VTM Not Supported Features
            2. 5.2.2.1.5.2 VTM Integration
            3. 5.2.2.1.5.3 VTM Functional Description
              1. 5.2.2.1.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.1.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.1.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.1.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.1.5.3.4 VTM Clocking
              5. 5.2.2.1.5.3.5 VTM Retention Interface
              6. 5.2.2.1.5.3.6 VTM ECC Aggregator
              7. 5.2.2.1.5.3.7 VTM Programming Model
                1. 5.2.2.1.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.1.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.1.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.1.5.3.8 AVS-Class0
          6. 5.2.2.1.6 Distributed Power Clock and Reset Controller (DPCR)
        2. 5.2.2.2 Power Control Modules
          1. 5.2.2.2.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.2.1.1 PSC Terminology
            2. 5.2.2.2.1.2 PSC Features
            3. 5.2.2.2.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.2.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.2.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.2.1.3.3 LPSC Dependences Overview
            4. 5.2.2.2.1.4 PSC: Power Domain and Module States
              1. 5.2.2.2.1.4.1 Power Domain States
              2. 5.2.2.2.1.4.2 Module States
              3. 5.2.2.2.1.4.3 Local Reset
            5. 5.2.2.2.1.5 PSC: Executing State Transitions
              1. 5.2.2.2.1.5.1 Power Domain State Transitions
              2. 5.2.2.2.1.5.2 Module State Transitions
              3. 5.2.2.2.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.2.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.2.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.2.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.2.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.2.1.7.2 A72SS Power State Transition
              3. 5.2.2.2.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.2.1.7.4 Power management features supported by C7x Corepac
              5. 5.2.2.2.1.7.5 C7x CorePac Clkstop/Powerdown/Disconnect Sequencing
              6. 5.2.2.2.1.7.6 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              7. 5.2.2.2.1.7.7 MCU Cortex-R5F Power Modes
              8. 5.2.2.2.1.7.8 C66x_DSPSS Power Sequences
          2. 5.2.2.2.2 Integrated Power Management (DMSC)
            1. 5.2.2.2.2.1 DMSC Power Management Overview
              1. 5.2.2.2.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 415
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1  WKUP and MCU Domains PLL Overview
        2. 5.4.5.2  MAIN Domain PLLs Overview
        3. 5.4.5.3  PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4  Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLLTS16FFCLVDESKEWC Type Output Clocks
              4. 5.4.5.4.1.2.4 PLL Lock
              5. 5.4.5.4.1.2.5 HSDIVIDER
              6. 5.4.5.4.1.2.6 ICG Module
              7. 5.4.5.4.1.2.7 PLL Power Down
              8. 5.4.5.4.1.2.8 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5  PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6  PLL and PLL Controller Connection
        7. 5.4.5.7  System Clocks Operating Frequency Ranges
        8. 5.4.5.8  Recommended Clock and Control Signal Transition Behavior
        9. 5.4.5.9  Interface Clock Specifications
        10. 5.4.5.10 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.10.1 PLL Initialization
            1. 5.4.5.10.1.1 Kick Protection Mechanism
            2. 5.4.5.10.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.10.1.3 PLL Programming Requirements
          2. 5.4.5.10.2 HSDIV PLL Programming
          3. 5.4.5.10.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.10.3.1 GO Operation
            2. 5.4.5.10.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.10.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
  8. 6 Processors and Accelerators
    1. 6.1  Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
    2. 6.2  Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
    3. 6.3  Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 Master Interfaces
          2. 6.3.3.3.2 Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Interrupts
        11. 6.3.3.11 R5FSS Debug and Trace
        12. 6.3.3.12 R5FSS Boot Options
    4. 6.4  C66x DSP Subsystem
    5. 6.5  C71x DSP Subsystem
      1. 6.5.1 C71SS Overview
        1. 6.5.1.1 C71SS Features
      2. 6.5.2 C71SS Integration
      3. 6.5.3 C71SS Functional Description
        1. 6.5.3.1 C71x DSP CPU
        2. 6.5.3.2 C71x DSP Matrix Multiply Accelerator
        3. 6.5.3.3 C71x DSP Cache Memory System
          1. 6.5.3.3.1 C71x DSP L1 Program Memory
          2. 6.5.3.3.2 C71x DSP L1 Data Memory
          3. 6.5.3.3.3 C71x DSP L2 Memory
        4. 6.5.3.4 C71x DSP Streaming Engine
        5. 6.5.3.5 C71x DSP CorePac Memory Management Unit
        6. 6.5.3.6 C71x DSP ECC Support
        7. 6.5.3.7 C71x DSP Boot Configuration
        8. 6.5.3.8 C71x DSP Power-Up/Down Sequences
        9. 6.5.3.9 C71x DSP Interrupt Control
    6. 6.6  Graphics Accelerator (GPU)
      1. 6.6.1 GPU Overview
        1. 6.6.1.1 GPU Features Overview
        2. 6.6.1.2 GPU Not Supported Features
      2. 6.6.2 GPU Integration
        1. 6.6.2.1 GPU Integration in MAIN Domain
      3. 6.6.3 GPU Functional Description
        1. 6.6.3.1 GPU Block Diagram
        2. 6.6.3.2 GPU Clock Configuration
        3. 6.6.3.3 GPU Reset
        4. 6.6.3.4 GPU Power Management
        5. 6.6.3.5 GPU Interrupt Requests
    7. 6.7  Multi-Standard HD Video Decoder (DECODER)
      1. 6.7.1 DECODER Overview
        1. 6.7.1.1 DECODER Features
        2. 6.7.1.2 DECODER Not Supported Features
      2. 6.7.2 DECODER Integration
        1. 6.7.2.1 DECODER Integration in MAIN Domain
      3. 6.7.3 DECODER Functional Description
        1. 6.7.3.1 DECODER Clock Configuration
        2. 6.7.3.2 DECODER Reset
        3. 6.7.3.3 DECODER Interrupts
    8. 6.8  Multi-Standard HD Video Encoder (ENCODER)
      1. 6.8.1 ENCODER Overview
        1. 6.8.1.1 ENCODER Features
        2. 6.8.1.2 ENCODER Not Supported Features
      2. 6.8.2 ENCODER Integration
        1. 6.8.2.1 ENCODER Integration in MAIN Domain
      3. 6.8.3 ENCODER Functional Description
        1. 6.8.3.1 ENCODER Clock Configuration
        2. 6.8.3.2 ENCODER Reset
        3. 6.8.3.3 ENCODER Interrupts
    9. 6.9  Vision Pre-processing Accelerator (VPAC)
      1. 6.9.1 VPAC Overview
        1. 6.9.1.1 VPAC Features
      2. 6.9.2 VPAC Integration
      3. 6.9.3 VPAC Subsystem Level
        1. 6.9.3.1 VPAC Subsystem Clocks
        2. 6.9.3.2 VPAC Subsystem Resets
        3. 6.9.3.3 VPAC Subsystem Interrupts
        4. 6.9.3.4 VPAC Subsystem SL2 Memory Infrastructure
        5. 6.9.3.5 VPAC Subsystem DMA Infrastructure
        6. 6.9.3.6 VPAC Subsystem Data Formats Support
        7. 6.9.3.7 VPAC Subsystem Debug Features
        8. 6.9.3.8 VPAC Subsystem Security Features
      4. 6.9.4 VPAC Vision Imaging Subsystem (VISS)
        1. 6.9.4.1 VISS Top Level
          1. 6.9.4.1.1  VISS Features
          2. 6.9.4.1.2  VISS Block Diagram
          3. 6.9.4.1.3  VISS Data Flow within VPAC
            1. 6.9.4.1.3.1 VISS On-the-fly Processing
              1. 6.9.4.1.3.1.1 Non-WDR or Companded WDR Sensors
            2. 6.9.4.1.3.2 VISS Memory to Memory Image Processing
          4. 6.9.4.1.4  VISS Data Formats Support
          5. 6.9.4.1.5  VISS VPORT Interface
          6. 6.9.4.1.6  VISS Submodule Integration Specifics
            1. 6.9.4.1.6.1 LSE Integration
            2. 6.9.4.1.6.2 GLBCE Integration
              1. 6.9.4.1.6.2.1 GLBCE Startup
              2. 6.9.4.1.6.2.2 GLBCE Bypass
          7. 6.9.4.1.7  VISS Stall Handling
            1. 6.9.4.1.7.1 Stall Handling for Streaming Mode
          8. 6.9.4.1.8  VISS Interrupts
            1. 6.9.4.1.8.1 Interrupts Merging
            2. 6.9.4.1.8.2 Handling of Configuration Error Interrupts
          9. 6.9.4.1.9  VISS Error Correcting Code (ECC) Support
          10. 6.9.4.1.10 VISS Programmer's Guide
            1. 6.9.4.1.10.1 VISS Initialization Sequence
            2. 6.9.4.1.10.2 VISS Configuration Restrictions
            3. 6.9.4.1.10.3 VISS Real-time Operating Requirements
        2. 6.9.4.2 VISS Load Store Engine (LSE)
        3. 6.9.4.3 VISS RAW Frond-End (RAWFE)
          1. 6.9.4.3.1 RAWFE Overview
            1. 6.9.4.3.1.1 RAWFE Supported Features
          2. 6.9.4.3.2 RAWFE Functional Description
            1. 6.9.4.3.2.1 RAWFE Functional Operation
            2. 6.9.4.3.2.2 RAWFE ECC for RAMs
          3. 6.9.4.3.3 RAWFE Interrupts
            1. 6.9.4.3.3.1 RAWFE CPU Interrupts
            2. 6.9.4.3.3.2 RAWFE Debug Events
          4. 6.9.4.3.4 RAWFE Sub-Modules Details
            1. 6.9.4.3.4.1 RAWFE Decompanding Block
              1. 6.9.4.3.4.1.1 RAWFE Mask & Shift
              2. 6.9.4.3.4.1.2 RAWFE Piece Wise Linear Operation
              3. 6.9.4.3.4.1.3 RAWFE Offset/WB-1 Block
              4. 6.9.4.3.4.1.4 RAWFE LUT Based compression
            2. 6.9.4.3.4.2 RAWFE WDR Merge Block
              1. 6.9.4.3.4.2.1 RAWFE WDR Motion Adaptive Merge (MA1 / MA2)
              2. 6.9.4.3.4.2.2 RAWFE Companding LUT
            3. 6.9.4.3.4.3 RAWFE Defective Pixel Correction (DPC) Block
              1. 6.9.4.3.4.3.1 RAWFE LUT Based DPC
              2. 6.9.4.3.4.3.2 RAWFE On-The-Fly (OTF) DPC
            4. 6.9.4.3.4.4 RAWFE Lens Shading Correction (LSC) and Digital Gain (DG) Block
              1. 6.9.4.3.4.4.1 RAWFE LSC Features Supported
              2. 6.9.4.3.4.4.2 RAWFE LSC Image Framing with Respect to Gain Map Samples
            5. 6.9.4.3.4.5 RAWFE Gain & Offset Block
            6. 6.9.4.3.4.6 RAWFE H3A
              1. 6.9.4.3.4.6.1  RAWFE H3A Overview
              2. 6.9.4.3.4.6.2  RAWFE H3A Top-Level Block Diagram
              3. 6.9.4.3.4.6.3  RAWFE H3A Line Framing Logic
              4. 6.9.4.3.4.6.4  RAWFE H3A Optional Preprocessing
              5. 6.9.4.3.4.6.5  RAWFE H3A Autofocus Engine
                1. 6.9.4.3.4.6.5.1 RAWFE H3A Paxel Extraction
                2. 6.9.4.3.4.6.5.2 RAWFE H3A Horizontal FV Calculator
                3. 6.9.4.3.4.6.5.3 RAWFE H3A HFV Accumulator
                4. 6.9.4.3.4.6.5.4 RAWFE H3A VFV Calculator
                5. 6.9.4.3.4.6.5.5 RAWFE H3A VFV Accumulator
              6. 6.9.4.3.4.6.6  RAWFE H3A AE/AWB Engine
                1. 6.9.4.3.4.6.6.1 RAWFE H3A Subsampler
                2. 6.9.4.3.4.6.6.2 RAWFE H3A Additional Black Row of AE/AWB Windows
                3. 6.9.4.3.4.6.6.3 RAWFE H3A Saturation Check
                4. 6.9.4.3.4.6.6.4 RAWFE H3A AE/AWB Accumulators
              7. 6.9.4.3.4.6.7  RAWFE H3A DMA Interface
              8. 6.9.4.3.4.6.8  RAWFE H3A Events and Status Checking
              9. 6.9.4.3.4.6.9  RAWFE H3A Interface Mux
              10. 6.9.4.3.4.6.10 RAWFE H3A interface to LSE
              11. 6.9.4.3.4.6.11 RAWFE H3A Erratas
          5. 6.9.4.3.5 RAWFE Programmer’s Guide
            1. 6.9.4.3.5.1 RAWFE Core programming details
            2. 6.9.4.3.5.2 RAWFE Initialization Sequence
            3. 6.9.4.3.5.3 RAWFE Real-time Оperating Requirements
        4. 6.9.4.4 VISS Spatial Noise Filter (NSF4V)
          1. 6.9.4.4.1 NSF4V Introduction
            1. 6.9.4.4.1.1 NSF4V Features
            2. 6.9.4.4.1.2 NSF4V Not Supported Features
          2. 6.9.4.4.2 NSF4V Overview
            1. 6.9.4.4.2.1 Decomposition Kernel Representation
          3. 6.9.4.4.3 NSF4V Lens Shading Correction Compensation
          4. 6.9.4.4.4 NSF4V Noise Threshold Adaptation to Local Image Intensity
        5. 6.9.4.5 VISS Global/Local Brightness and Contrast Enhancement (GLBCE) Module
          1. 6.9.4.5.1 GLBCE Overview
          2. 6.9.4.5.2 GLBCE Interface
          3. 6.9.4.5.3 GLBCE Core
            1. 6.9.4.5.3.1 GLBCE Core Key Parameters
            2. 6.9.4.5.3.2 GLBCE Iridix Strength Calculation
            3. 6.9.4.5.3.3 GLBCE Iridix Configuration Registers
              1. 6.9.4.5.3.3.1  GLBCE Iridix Frame Width
              2. 6.9.4.5.3.3.2  GLBCE Iridix Frame Height
              3. 6.9.4.5.3.3.3  GLBCE Iridix Control 0
              4. 6.9.4.5.3.3.4  GLBCE Iridix Control 1
              5. 6.9.4.5.3.3.5  GLBCE Iridix Strength
              6. 6.9.4.5.3.3.6  GLBCE Iridix Variance
              7. 6.9.4.5.3.3.7  GLBCE Iridix Dither
              8. 6.9.4.5.3.3.8  GLBCE Iridix Amplification Limit
              9. 6.9.4.5.3.3.9  GLBCE Iridix Slope Min and Max
              10. 6.9.4.5.3.3.10 GLBCE Iridix Black Level
              11. 6.9.4.5.3.3.11 GLBCE Iridix White Level
              12. 6.9.4.5.3.3.12 GLBCE Iridix Asymmetry Function Look-up-table
              13. 6.9.4.5.3.3.13 GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
              14. 6.9.4.5.3.3.14 GLBCE Iridix WDR Look-up-table
          4. 6.9.4.5.4 GLBCE Embedded Memory
          5. 6.9.4.5.5 GLBCE General Processing
          6. 6.9.4.5.6 GLBCE Continuous Frame Processing
          7. 6.9.4.5.7 GLBCE Single Image Processing
        6. 6.9.4.6 VISS Flexible Color Processing (FCP) Module
          1. 6.9.4.6.1 FCP Overview
            1. 6.9.4.6.1.1 FCP Features Supported
          2. 6.9.4.6.2 FCP Functional Description
          3. 6.9.4.6.3 FCP Submodule Details
            1. 6.9.4.6.3.1 Flexible CFA / Demosaicing
              1. 6.9.4.6.3.1.1 Feature-set
              2. 6.9.4.6.3.1.2 Block Diagram of Flexible CFA
                1. 6.9.4.6.3.1.2.1 Gradient/Threshold Calculation
                2. 6.9.4.6.3.1.2.2 Software Controlled Direction Selection
            2. 6.9.4.6.3.2 Edge Enhancer Module Wrapper (WEE)
              1. 6.9.4.6.3.2.1 EE - Edge Enhancer Block
            3. 6.9.4.6.3.3 Flexible Color Conversion (CC)
              1. 6.9.4.6.3.3.1 Interface Mux
              2. 6.9.4.6.3.3.2 Color Conversion (CCM-1)
              3. 6.9.4.6.3.3.3 RGB to HSX Conversion
                1. 6.9.4.6.3.3.3.1 Weighted Average Block
                2. 6.9.4.6.3.3.3.2 Saturation Block
                3. 6.9.4.6.3.3.3.3 Division Block
                4. 6.9.4.6.3.3.3.4 LUT Based 12 to 8 Downsampling
              4. 6.9.4.6.3.3.4 Histogram
              5. 6.9.4.6.3.3.5 Contrast Stretch / Gamma
              6. 6.9.4.6.3.3.6 RGB-YUV Conversion
            4. 6.9.4.6.3.4 444-422/420 Chroma Down-sampler
          4. 6.9.4.6.4 FCP Interrupts
          5. 6.9.4.6.5 FCP Programmer’s Guide
            1. 6.9.4.6.5.1 HWA Core Programming Details
            2. 6.9.4.6.5.2 HWA HTS Programming Details
            3. 6.9.4.6.5.3 HWA Data Transfer Programming Details
            4. 6.9.4.6.5.4 Initialization Sequence
            5. 6.9.4.6.5.5 Real-time Operating Requirements
            6. 6.9.4.6.5.6 Power Up/Down Sequence
        7. 6.9.4.7 VISS Edge Enhancer (EE)
          1. 6.9.4.7.1 Edge Enhancer Introduction
            1. 6.9.4.7.1.1 Edge Enhancer Filter
            2. 6.9.4.7.1.2 Edge Sharpener Filter
            3. 6.9.4.7.1.3 Merge Block
          2. 6.9.4.7.2 Edge Enhancer Programming Model
      5. 6.9.5 VPAC Lens Distortion Correction (LDC) Module
        1. 6.9.5.1 LDC Overview
          1. 6.9.5.1.1 LDC Features
        2. 6.9.5.2 LDC Functional Description
          1. 6.9.5.2.1  LDC Block Diagram
          2. 6.9.5.2.2  LDC Clocks
          3. 6.9.5.2.3  LDC Interrupts
            1. 6.9.5.2.3.1 LDC Interrupt Events Description
              1. 6.9.5.2.3.1.1 PIX_IBLK_OUTOFBOUND
              2. 6.9.5.2.3.1.2 MESH_IBLK_OUTOFBOUND
              3. 6.9.5.2.3.1.3 IFR_OUTOFBOUND
              4. 6.9.5.2.3.1.4 INT_SZOVF
              5. 6.9.5.2.3.1.5 VPAC_LDC_FR_DONE_EVT
              6. 6.9.5.2.3.1.6 VPAC_LDC_SL2_WR_ERR
              7. 6.9.5.2.3.1.7 PIX_IBLK_MEMOVF
              8. 6.9.5.2.3.1.8 MESH_IBLK_MEMOVF
              9. 6.9.5.2.3.1.9 VPAC_LDC_VBUSM_RD_ERR
          4. 6.9.5.2.4  LDC Affine Transform
          5. 6.9.5.2.5  LDC Perspective Transformation
          6. 6.9.5.2.6  LDC Lens Distortion Back Mapping
            1. 6.9.5.2.6.1 LDC Mesh Table Storage Format
          7. 6.9.5.2.7  LDC Pixel Interpolation
          8. 6.9.5.2.8  LDC Buffer Management
            1. 6.9.5.2.8.1 LDC Buffer Management
          9. 6.9.5.2.9  LDC Multi Region with Variable Block size
            1. 6.9.5.2.9.1 LDC Region Skip Feature
            2. 6.9.5.2.9.2 LDC Support for sub-set of 3x3 regions
            3. 6.9.5.2.9.3 LDC Limitations of Multi Region Scheme
            4. 6.9.5.2.9.4 LDC Multi Region Block Constrains
          10. 6.9.5.2.10 LDC Multi-pass Frame processing
          11. 6.9.5.2.11 LDC Input/Output Data Formats
          12. 6.9.5.2.12 LDC YUV422 to YUV420 Conversion
          13. 6.9.5.2.13 LDC SL2 Interface (LSE)
            1. 6.9.5.2.13.1 LDC PSA (Parallel Signature Analysis)
          14. 6.9.5.2.14 LDC LUT Mapped Dual Output
          15. 6.9.5.2.15 LDC Band Width Controller
          16. 6.9.5.2.16 LDC Input Block Fetch Limit
          17. 6.9.5.2.17 LDC HTS Interface
          18. 6.9.5.2.18 LDC VBUSM Read Interface
        3. 6.9.5.3 LDC Programmers Guide
          1. 6.9.5.3.1 LDC Programming Geometric Distortion Mode
          2. 6.9.5.3.2 LDC Programming Rotational Video Stabilization (Affine Transformation)
          3. 6.9.5.3.3 LDC Programming Perspective Transformation
          4. 6.9.5.3.4 LDC Programming LSE
          5. 6.9.5.3.5 LDC Programming Restrictions and Special Cases
      6. 6.9.6 VPAC Multi-Scaler (MSC)
        1. 6.9.6.1 MSC Overview
          1. 6.9.6.1.1 MSC Features
          2. 6.9.6.1.2 MSC Not Supported Features
        2. 6.9.6.2 MSC Functional Description
          1. 6.9.6.2.1 MSC Functional Overview
            1. 6.9.6.2.1.1 MSC Submodule Details
              1. 6.9.6.2.1.1.1 MSC Load Store Engine (MSC_LSE)
                1. 6.9.6.2.1.1.1.1 MSC_LSE Overview
                  1. 9.6.2.1.1.1.1.1 MSC_LSE Features
                2. 6.9.6.2.1.1.1.2 MSC_LSE Internal Data Loopback Channel
                3. 6.9.6.2.1.1.1.3 MSC_LSE PSA Support
                4. 6.9.6.2.1.1.1.4 MSC_LSE Feature Detailed Description
              2. 6.9.6.2.1.1.2 MSC_CORE (HWA Core)
                1. 6.9.6.2.1.1.2.1 MSC_CORE Overview
                2. 6.9.6.2.1.1.2.2 Polyphase Filter of Vertical/Horizontal Resizers
                  1. 9.6.2.1.1.2.2.1 Filter Data Path Logic
                  2. 9.6.2.1.1.2.2.2 Filter Parameters
                  3. 9.6.2.1.1.2.2.3 Single-Phase Filter Parameters
                  4. 9.6.2.1.1.2.2.4 Interleaved Mode Handling
                  5. 9.6.2.1.1.2.2.5 Input Skip Line Support
                3. 6.9.6.2.1.1.2.3 Scaler Filter Thread Mapping
                4. 6.9.6.2.1.1.2.4 Filter Coefficients
                  1. 9.6.2.1.1.2.4.1 Filter Coefficient Parameter Configuration
                  2. 9.6.2.1.1.2.4.2 3/4/5-Tap Filter Configuration
                5. 6.9.6.2.1.1.2.5 Input/Output ROI Trimmers
          2. 6.9.6.2.2 Resizer Algorithm Details
            1. 6.9.6.2.2.1 Multiple Scales Generations
            2. 6.9.6.2.2.2 Polyphase Filter
              1. 6.9.6.2.2.2.1 Interpolation/Resampling
              2. 6.9.6.2.2.2.2 Phase Calculation and Re-sampler
              3. 6.9.6.2.2.2.3 Shared Coefficient Buffers
              4. 6.9.6.2.2.2.4 Border Pixel Padding
            3. 6.9.6.2.2.3 ROI Handling
          3. 6.9.6.2.3 MSC Data Formats Supported
        3. 6.9.6.3 MSC Interrupt Conditions
          1. 6.9.6.3.1 CPU Interrupts
          2. 6.9.6.3.2 Interrupt Event Description
            1. 6.9.6.3.2.1 VPAC_MSC_LSE_FR_DONE_EVT_0/1 Events
            2. 6.9.6.3.2.2 VPAC_MSC_LSE_SL2_RD_ERR Interrupt Event
            3. 6.9.6.3.2.3 VPAC_MSC_LSE_SL2_WR_ERR Interrupt Event
        4. 6.9.6.4 MSC Performance
        5. 6.9.6.5 MSC Clocking
        6. 6.9.6.6 MSC Reset
        7. 6.9.6.7 MSC Programmer’s Guide
          1. 6.9.6.7.1 Programming Model
            1. 6.9.6.7.1.1 MSC Programming Guidelines
            2. 6.9.6.7.1.2 MSC_Core Programming Details
            3. 6.9.6.7.1.3 MSC_LSE Programming Details
              1. 6.9.6.7.1.3.1 Input Thread Configuration:
              2. 6.9.6.7.1.3.2 Output Channel Configuration
            4. 6.9.6.7.1.4 MSC HTS Programming Details
            5. 6.9.6.7.1.5 MSC Data Transfer Programming Details
            6. 6.9.6.7.1.6 LSE Interrupt Programming
          2. 6.9.6.7.2 Initialization Sequence
          3. 6.9.6.7.3 Real-Time Operating Requirements
          4. 6.9.6.7.4 Power Up/Down Sequence
      7. 6.9.7 VPAC Noise Filter (NF)
        1. 6.9.7.1 NF Overview
          1. 6.9.7.1.1 NF Supported Features
        2. 6.9.7.2 NF Functional Description
          1. 6.9.7.2.1 Functional Operation
            1. 6.9.7.2.1.1 Overview
            2. 6.9.7.2.1.2 Algorithm Details
        3. 6.9.7.3 NF Interrupts
          1. 6.9.7.3.1 CPU Interrupts
          2. 6.9.7.3.2 Interrupt Event Description
            1. 6.9.7.3.2.1 NF_FRAME_DONE Event
            2. 6.9.7.3.2.2 NF_SL2_READ_ERROR Event
            3. 6.9.7.3.2.3 NF_SL2_WRITE_ERROR Event
        4. 6.9.7.4 NF Submodule Details
          1. 6.9.7.4.1 NF_CFG
          2. 6.9.7.4.2 NF_LSE
            1. 6.9.7.4.2.1 NF_LSE Overview
            2. 6.9.7.4.2.2 NF_LSE Feature Detailed Description
          3. 6.9.7.4.3 Synchronization With HTS
          4. 6.9.7.4.4 Noise Filter Core Block Diagram
            1. 6.9.7.4.4.1 Space Weight Details
            2. 6.9.7.4.4.2 Weight Calculation Logic
              1. 6.9.7.4.4.2.1 Combined LUT For Space And Range Weights
            3. 6.9.7.4.4.3 Reciprocal Calculation Logic
            4. 6.9.7.4.4.4 Border Handling
              1. 6.9.7.4.4.4.1 Border Handling (Simple)
          5. 6.9.7.4.5 Usage As Generic 2D Filter Engine
          6. 6.9.7.4.6 Adaptive Bilateral Weight Support
          7. 6.9.7.4.7 Chroma Handling (Interleaved Mode)
        5. 6.9.7.5 NF Programmer’s Guide
          1. 6.9.7.5.1 Programming Model
            1. 6.9.7.5.1.1 HWA Core Programming Details
            2. 6.9.7.5.1.2 NF SL2 Wrapper Interface Programming Details
            3. 6.9.7.5.1.3 HWA HTS Programming Details
            4. 6.9.7.5.1.4 HWA Data Transfer Programming Details
    10. 6.10 Depth and Motion Perception Accelerator (DMPAC)
      1. 6.10.1 DMPAC Overview
        1. 6.10.1.1 DMPAC Features
      2. 6.10.2 DMPAC Integration
      3. 6.10.3 DMPAC Functional Description
        1. 6.10.3.1  DMPAC Block Diagram
        2. 6.10.3.2  DMPAC Data Formats and Image Resolution
          1. 6.10.3.2.1 Resolution and Frame Rate
          2. 6.10.3.2.2 Input Data Formats
        3. 6.10.3.3  DMPAC Top Level Data Flow
        4. 6.10.3.4  DMPAC Stereo Functional Overview
          1. 6.10.3.4.1  Stereo Processing Dataflow
          2. 6.10.3.4.2  Disparity Range
          3. 6.10.3.4.3  Epipolar Rectification
          4. 6.10.3.4.4  Disparity Search Method
          5. 6.10.3.4.5  Cost Computation Method
          6. 6.10.3.4.6  Cost Plane Compression Method
          7. 6.10.3.4.7  Sub-Pixel Interpolation Method
          8. 6.10.3.4.8  Raw Disparity Output Cleaning Method
          9. 6.10.3.4.9  Confidence Score Computation Method
          10. 6.10.3.4.10 Disparity Map Post Filtering Method
          11. 6.10.3.4.11 Disparity Output Data Packing Format
        5. 6.10.3.5  DMPAC Optical Flow Functional Overview
          1. 6.10.3.5.1  Optical Flow Processing Dataflow
          2. 6.10.3.5.2  Flow Vector Range
          3. 6.10.3.5.3  Block Matching Process
          4. 6.10.3.5.4  Image Pyramid Generation Method
          5. 6.10.3.5.5  Cost Computation Method
          6. 6.10.3.5.6  Sub-Pixel Refinement Method
          7. 6.10.3.5.7  Confidence Score Computation Method
          8. 6.10.3.5.8  Flow Vector Post Filtering Method
          9. 6.10.3.5.9  Flow Vector Output Data Packing Format
          10. 6.10.3.5.10 Sparse Optical Flow Support
        6. 6.10.3.6  DMPAC Format Conversion (FOCO) Module Operation
          1. 6.10.3.6.1 FOCO Implementation Details
          2. 6.10.3.6.2 FOCO Core Details
        7. 6.10.3.7  DMPAC Clocks
        8. 6.10.3.8  DMPAC Resets
        9. 6.10.3.9  DMPAC Interrupts
        10. 6.10.3.10 DMPAC SL2 Memory Subsystem
        11. 6.10.3.11 DMPAC Common DMA
        12. 6.10.3.12 DMPAC Messaging and Control
          1. 6.10.3.12.1 DOF Node Scheduler
          2. 6.10.3.12.2 SDE Node Scheduler
        13. 6.10.3.13 DMPAC Hardware Security
          1. 6.10.3.13.1 Configuration Interconnect
          2. 6.10.3.13.2 SL2 Interconnect
        14. 6.10.3.14 DMPAC Debug
        15. 6.10.3.15 DMPAC Internal Diagnostic Features
        16. 6.10.3.16 DMPAC Memory Error Protection
      4. 6.10.4 DMPAC Programming Guide
        1. 6.10.4.1 DMPAC Optical Flow Initialization Sequence - 12-bit Packed Input Pixel Data
          1. 6.10.4.1.1 Optical Flow 12bb - DMPAC Top Level Configuration
          2. 6.10.4.1.2 Optical Flow 12bb - UTC Configuration
            1. 6.10.4.1.2.1 Reference Frame Growing Window Fetch
            2. 6.10.4.1.2.2 Current Frame Growing Window Fetch
            3. 6.10.4.1.2.3 Temporal Predictor Fetch
            4. 6.10.4.1.2.4 Pyramidal Predictor Fetch
            5. 6.10.4.1.2.5 Sparse Optical Flow Binary Map Fetch
            6. 6.10.4.1.2.6 Flow Vector Output
          3. 6.10.4.1.3 Optical Flow 12bb - HTS Configuration
        2. 6.10.4.2 DMPAC Stereo Disparity Initialization Sequence - 12-bit Packed Input Pixel Data
          1. 6.10.4.2.1 Stereo Disparity 12bpp - DMPAC Top Configuration
          2. 6.10.4.2.2 Stereo Disparity 12bpp - DMA Configuration
            1. 6.10.4.2.2.1 Reference Frame Growing Window Fetch
            2. 6.10.4.2.2.2 Base Frame Growing Window Fetch
            3. 6.10.4.2.2.3 Stereo Disparity Output
          3. 6.10.4.2.3 Stereo Disparity 12bpp - HTS Configuration
        3. 6.10.4.3 DMPAC End of Pipeline Processing
        4. 6.10.4.4 DMPAC Debug Restrictions
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 1029
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
    3. 8.3 Virtualization Subsystem (VirtSS)
      1. 8.3.1 VirtSS Overview
        1. 8.3.1.1 VirtSS Features
        2. 8.3.1.2 Functional Description
          1. 8.3.1.2.1  Ports
          2. 8.3.1.2.2  CBASS
          3. 8.3.1.2.3  PAT
            1. 8.3.1.2.3.1 Bandwidth Splitting
          4. 8.3.1.2.4  PVU
            1. 8.3.1.2.4.1 Bandwidth Splitting
          5. 8.3.1.2.5  TBU
            1. 8.3.1.2.5.1 Bandwidth Splitting
            2. 8.3.1.2.5.2 Initialization Delay Requirement
          6. 8.3.1.2.6  TCU
          7. 8.3.1.2.7  DTI Interconnect
          8. 8.3.1.2.8  External DTI Ports
          9. 8.3.1.2.9  DMA Split
          10. 8.3.1.2.10 Port Routing Rules
        3. 8.3.1.3 VirtSS Configuration
          1. 8.3.1.3.1 PAT Parameters
          2. 8.3.1.3.2 PVU Parameters
          3. 8.3.1.3.3 TBU Parameters
          4. 8.3.1.3.4 TCU Parameters
          5. 8.3.1.3.5 ECC Aggregator Parameters
        4. 8.3.1.4 Theory of Operation
          1. 8.3.1.4.1 TBU Address Translation Module
          2. 8.3.1.4.2 DTI
          3. 8.3.1.4.3 TCU
          4. 8.3.1.4.4 1153
          5. 8.3.1.4.5 PAT Address Translation Module
            1. 8.3.1.4.5.1 Run-Time PAT Configuration
          6. 8.3.1.4.6 PVU Address Translation Module
      2. 8.3.2 Peripheral Virtualization Unit (PVU)
        1. 8.3.2.1 PVU Overview
          1. 8.3.2.1.1 PVU Features
          2. 8.3.2.1.2 PVU Parameters
          3. 8.3.2.1.3 PVU Not Supported Features
        2. 8.3.2.2 PVU Integration
        3. 8.3.2.3 PVU Functional Description
          1. 8.3.2.3.1  Functional Operation Overview
          2. 8.3.2.3.2  PVU Channels
          3. 8.3.2.3.3  TLB
          4. 8.3.2.3.4  TLB Entry
          5. 8.3.2.3.5  TLB Selection
          6. 8.3.2.3.6  DMA Classes
          7. 8.3.2.3.7  General virtIDs
          8. 8.3.2.3.8  TLB Lookup
          9. 8.3.2.3.9  TLB Miss
          10. 8.3.2.3.10 Multiple Matching Entries
          11. 8.3.2.3.11 TLB Disable
          12. 8.3.2.3.12 TLB Chaining
          13. 8.3.2.3.13 TLB Permissions
          14. 8.3.2.3.14 Translation
          15. 8.3.2.3.15 Memory Attributes
          16. 8.3.2.3.16 Faulted Transactions
          17. 8.3.2.3.17 Non-Virtual Transactions
          18. 8.3.2.3.18 Allowed virtIDs
          19. 8.3.2.3.19 Software Control
          20. 8.3.2.3.20 Fault Logging
          21. 8.3.2.3.21 Alignment Restrictions
      3. 8.3.3 Page Based Address Translation Unit (PAT)
        1. 8.3.3.1 PAT Overview
          1. 8.3.3.1.1 PAT Features
          2. 8.3.3.1.2 PAT Parameters
          3. 8.3.3.1.3 PAT Not Supported Features
        2. 8.3.3.2 PAT Integration
        3. 8.3.3.3 PAT Functional Description
          1. 8.3.3.3.1 Functional Operation Overview
          2. 8.3.3.3.2 Page Table
          3. 8.3.3.3.3 Alignment
          4. 8.3.3.3.4 Page Enables
          5. 8.3.3.3.5 Table Arbitration
          6. 8.3.3.3.6 Programming
          7. 8.3.3.3.7 Scratch RAM
          8. 8.3.3.3.8 Error Reporting
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
          3. 9.2.1.1.3 GIC Configuration Summary
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC Interrupt Edge Detection
          8. 9.2.1.3.8 GIC AXI2VBUSM and VBUSM2AXI Bridges
      2. 9.2.2 Cluster Level Event Controller (CLEC)
        1. 9.2.2.1 CLEC Overview
        2. 9.2.2.2 CLEC Integration
        3. 9.2.2.3 CLEC Functional Description
          1. 9.2.2.3.1 CLEC Interrupt Event Routing
          2. 9.2.2.3.2 CLEC Virtualization, Isolation and Access Control
          3. 9.2.2.3.3 CLEC Memory Protection
          4. 9.2.2.3.4 CLEC ECC Support
          5. 9.2.2.3.5 CLEC Intra-Core Communication
          6. 9.2.2.3.6 CLEC Event Maps
            1. 9.2.2.3.6.1 CLEC Output Event Routing
            2. 9.2.2.3.6.2 CLEC Input Event Map
            3. 9.2.2.3.6.3 CLEC ESM Event Routing
            4. 9.2.2.3.6.4 CLEC C7x DSP Input Event Map
      3. 9.2.3 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
        5. 9.3.2.5 C66SS0_INTRTR0 Integration
        6. 9.3.2.6 C66SS1_INTRTR0 Integration
        7. 9.3.2.7 R5FSS0_INTRTR0 Integration
        8. 9.3.2.8 R5FSS1_INTRTR0 Integration
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1  COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
        2. 9.4.3.2  R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3  R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4  R5FSS1_CORE0 Interrupt Map
        5. 9.4.3.5  R5FSS1_CORE1 Interrupt Map
        6. 9.4.3.6  R5FSS0_INTRTR0 Interrupt Map
        7. 9.4.3.7  R5FSS1_INTRTR0 Interrupt Map
        8. 9.4.3.8  C66SS0 Interrupt Map
        9. 9.4.3.9  C66SS1 Interrupt Map
        10. 9.4.3.10 C66SS0_INTRTR0 Interrupt Map
        11. 9.4.3.11 C66SS1_INTRTR0 Interrupt Map
        12. 9.4.3.12 PRU-ICSSG0 Interrupt Map
        13. 9.4.3.13 PRU-ICSSG1 Interrupt Map
        14. 9.4.3.14 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        15. 9.4.3.15 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        16. 9.4.3.16 GPIOMUX_INTRTR0 Interrupt Map
        17. 9.4.3.17 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 DMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  1378
        5. 10.1.3.5  UDMA Internal Transmit Channel Teardown (All Packet Types)
        6. 10.1.3.6  UDMA External Transmit Channel Setup
        7. 10.1.3.7  UDMA Transmit External Channel Teardown
        8. 10.1.3.8  UDMA-P Transmit Channel Pause
        9. 10.1.3.9  1383
        10. 10.1.3.10 UDMA-P Transmit Operation (Host Packet Type)
        11. 10.1.3.11 UDMA-P Transmit Operation (Monolithic Packet)
        12. 10.1.3.12 UDMA Transmit Operation (TR Packet)
        13. 10.1.3.13 UDMA Transmit Operation (Direct TR)
        14. 10.1.3.14 UDMA Transmit Error/Exception Handling
          1. 10.1.3.14.1 Null Icnt0 Error
          2. 10.1.3.14.2 Unsupported TR Type
          3. 10.1.3.14.3 Bus Errors
        15. 10.1.3.15 UDMA Receive Channel Setup (All Packet Types)
        16. 10.1.3.16 UDMA Receive Channel Teardown
        17. 10.1.3.17 UDMA-P Receive Channel Pause
        18. 10.1.3.18 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        19. 10.1.3.19 UDMA-P Receive FlowID Firewall Operation
        20. 10.1.3.20 UDMA-P Receive Operation (Host Packet)
        21. 10.1.3.21 UDMA-P Receive Operation (Monolithic Packet)
        22. 10.1.3.22 UDMA Receive Operation (TR Packet)
        23. 10.1.3.23 UDMA Receive Operation (Direct TR)
        24. 10.1.3.24 UDMA Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Conditions
            1. 10.1.3.24.1.1 Bus Errors
            2. 10.1.3.24.1.2 Null Icnt0 Error
            3. 10.1.3.24.1.3 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions Exception Conditions
            1. 10.1.3.24.2.1 Descriptor Starvation
            2. 10.1.3.24.2.2 Protocol Errors
            3. 10.1.3.24.2.3 Dropped Packets
            4. 10.1.3.24.2.4 Reception of EOL Delimiter
            5. 10.1.3.24.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.24.2.6 EOP Asserted Late (Long Packets)
        25. 10.1.3.25 UTC Operation
        26. 10.1.3.26 UTC Receive Error/Exception Handling
          1. 10.1.3.26.1 Error Handling
            1. 10.1.3.26.1.1 Null Icnt0 Error
            2. 10.1.3.26.1.2 Unsupported TR Type
          2. 10.1.3.26.2 Exception Conditions
            1. 10.1.3.26.2.1 Reception of EOL Delimiter
            2. 10.1.3.26.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.26.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
          5. 10.2.1.2.5 1430
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1448
        3. 10.2.2.3 MCU NAVSS Functional Description
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA0 (PDMA_AASRC) Features
            6. 10.3.1.1.1.6  PDMA2 (PDMA_DEBUG_CCMCU) Features
            7. 10.3.1.1.1.7  PDMA3 (PDMA_DEBUG_C66) Features
            8. 10.3.1.1.1.8  PDMA5 (PDMA_MCAN) Features
            9. 10.3.1.1.1.9  PDMA6 (PDMA_MCASP_G0) Features
            10. 10.3.1.1.1.10 PDMA7 (PDMA_MCASP_G1) Features
            11. 10.3.1.1.1.11 PDMA8 (PDMA_MISC_G0) Features
            12. 10.3.1.1.1.12 PDMA9 (PDMA_MISC_G1) Features
            13. 10.3.1.1.1.13 PDMA10 (PDMA_MISC_G2) Features
            14. 10.3.1.1.1.14 PDMA11 (PDMA_MISC_G3) Features
            15. 10.3.1.1.1.15 PDMA13 (PDMA_USART_G0) Features
            16. 10.3.1.1.1.16 PDMA14 (PDMA_USART_G1) Features
            17. 10.3.1.1.1.17 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1690
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1699
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1  PDMA_AASRC Event Map
          2. 10.3.2.2.2  PDMA_DEBUG_CCMCU Event Map
          3. 10.3.2.2.3  PDMA_DEBUG_C66 Event Map
          4. 10.3.2.2.4  PDMA_MCAN Event Map
          5. 10.3.2.2.5  PDMA_MCASP_G0 Event Map
          6. 10.3.2.2.6  PDMA_MCASP_G1 Event Map
          7. 10.3.2.2.7  PDMA_MISC_G0 Event Map
          8. 10.3.2.2.8  PDMA_MISC_G1 Event Map
          9. 10.3.2.2.9  PDMA_MISC_G2 Event Map
          10. 10.3.2.2.10 PDMA_MISC_G3 Event Map
          11. 10.3.2.2.11 PDMA_USART_G0 Event Map
          12. 10.3.2.2.12 PDMA_USART_G1 Event Map
          13. 10.3.2.2.13 PDMA_USART_G2 Event Map
    4. 10.4 Data Routing Unit (DRU)
      1. 10.4.1 DRU Overview
      2. 10.4.2 DRU Integration
        1. 10.4.2.1 DRU Integration in MAIN Domain
      3. 10.4.3 DRU Functional Description
        1. 10.4.3.1 DRU Basic Functionality
          1. 10.4.3.1.1 Queues
          2. 10.4.3.1.2 Channel Configuration
            1. 10.4.3.1.2.1 Non-realtime Channel Configuration
            2. 10.4.3.1.2.2 Realtime Channel Configuration
          3. 10.4.3.1.3 TR Submission
            1. 10.4.3.1.3.1 Direct TR Submission
            2. 10.4.3.1.3.2 PSI-L TR Submission
          4. 10.4.3.1.4 TR Removal from Channel
          5. 10.4.3.1.5 Channel Tear Down
            1. 10.4.3.1.5.1 Tear Down Completion
        2. 10.4.3.2 DRU Output Events
        3. 10.4.3.3 DRU Address Fetch Algorithm, TR and CR Formats
          1. 10.4.3.3.1 Transpose
          2. 10.4.3.3.2 Circular Buffering
        4. 10.4.3.4 DRU Firewalls
        5. 10.4.3.5 DRU Errors
        6. 10.4.3.6 DRU Configurations
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1  CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2  TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3  PRU_ICSSG0 Sync Event Map
        4. 11.3.3.4  PRU_ICSSG1 Sync Event Map
        5. 11.3.3.5  NAVSS0 Sync Event Map
        6. 11.3.3.6  PCIE0 Sync Event Map
        7. 11.3.3.7  PCIE1 Sync Event Map
        8. 11.3.3.8  PCIE2 Sync Event Map
        9. 11.3.3.9  PCIE3 Sync Event Map
        10. 11.3.3.10 MCU_CPSW0 Sync Event Map
        11. 11.3.3.11 CPSW0 Sync Event Map
        12. 11.3.3.12 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1  General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1916
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1969
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
    2. 12.2  High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 2356
                1. 12.2.1.4.6.10.1.1 2357
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2456
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2484
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_9G
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2723
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2751
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_9G Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Subsystem Conventional Reset
            2. 12.2.3.4.2.2 PCIe Subsystem Function Level Reset
            3. 12.2.3.4.2.3 Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.1.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.1.2 MSI and MSI-X Interrupt Generation
            2. 12.2.3.4.4.2 PCIe Interrupt Reception in EP Mode
              1. 12.2.3.4.4.2.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.2.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.2.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.2.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.2.5 PTM Valid Interrupt
            3. 12.2.3.4.4.3 PCIe Interrupt Generation in RP Mode
            4. 12.2.3.4.4.4 PCIe Interrupt Reception in RP Mode
              1. 12.2.3.4.4.4.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.4.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.4.3 Advanced Error Reporting Interrupt
            5. 12.2.3.4.4.5 PCIe Interrupt Reception in RP and EP Mode
              1. 12.2.3.4.4.5.1 PCIe Local Interrupt
              2. 12.2.3.4.4.5.2 PHY Interrupt
              3. 12.2.3.4.4.5.3 Link down Interrupt
              4. 12.2.3.4.4.5.4 Transaction Error Interrupts
              5. 12.2.3.4.4.5.5 Power Management Event Interrupt
              6. 12.2.3.4.4.5.6 Active Internal Diagnostics Interrupts
            6. 12.2.3.4.4.6 ECC Aggregator Interrupts
            7. 12.2.3.4.4.7 CPTS Interrupts
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in Root Port Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in End Point Mode
          6. 12.2.3.4.6  PCIe Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 EP SR-IOV support
            2. 12.2.3.4.8.2 RP ATS support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC inversion
          14. 12.2.3.4.14 LTSSM State Encoding
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
      5. 12.2.5 2-L Serializer/Deserializer (SerDes)
        1. 12.2.5.1 2-L SerDes Overview
          1. 12.2.5.1.1 2-L SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 2-L SerDes Environment
          1. 12.2.5.2.1 2-L SerDes I/Os
        3. 12.2.5.3 2-L SerDes Integration
          1. 12.2.5.3.1 2-L WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Internal Reference Clock Selection
        4. 12.2.5.4 2-L SerDes Functional Description
          1. 12.2.5.4.1 2-L SerDes Block Diagram
      6. 12.2.6 4-L Serializer/Deserializer (SerDes)
        1. 12.2.6.1 4-L SerDes Overview
          1. 12.2.6.1.1 4-L SerDes Features
          2. 12.2.6.1.2 Industry Standards Compatibility
        2. 12.2.6.2 4-L SerDes Environment
          1. 12.2.6.2.1 4-L SerDes I/Os
        3. 12.2.6.3 4-L SerDes Integration
          1. 12.2.6.3.1 4-L WIZ Settings
            1. 12.2.6.3.1.1 Interface Selection
            2. 12.2.6.3.1.2 Internal Reference Clock Selection
        4. 12.2.6.4 4-L SerDes Functional Description
          1. 12.2.6.4.1 4-L SerDes Block Diagram
    3. 12.3  Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Read Operations
            1. 12.3.1.4.4.1 OSPI Read Pipeline Mode
          5. 12.3.1.4.5 FSS Memory Address Translation
          6. 12.3.1.4.6 FSS0 and FSS1 Regions
            1. 12.3.1.4.6.1 FSS0 and FSS1 Regions Boot Size Configuration
          7. 12.3.1.4.7 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2956
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 3163
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
      6. 12.3.6 Multimedia Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 3241
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
      7. 12.3.7 Universal Flash Storage (UFS) Interface
        1. 12.3.7.1 UFS Overview
          1. 12.3.7.1.1 UFS Features
        2. 12.3.7.2 UFS Environment
        3. 12.3.7.3 UFS Integration
          1. 12.3.7.3.1 UFS Integration in MAIN Domain
        4. 12.3.7.4 UFS Functional Description
          1. 12.3.7.4.1 UFS Block Diagrams
          2. 12.3.7.4.2 UFS ECC Support
        5. 12.3.7.5 UFS Programming Guide
          1. 12.3.7.5.1 UFS Start-Up Sequence
            1. 12.3.7.5.1.1 UniPro Initialization
              1. 12.3.7.5.1.1.1 UniPro Layer 2 Configuration
                1. 12.3.7.5.1.1.1.1 Layer 2 Threshold Value Calculation
                2. 12.3.7.5.1.1.1.2 DL_TC0TXFCThreshold
                3. 12.3.7.5.1.1.1.3 DL_AFC0CreditThreshold
                4. 12.3.7.5.1.1.1.4 DL_TC0OutAckThreshold
                5. 12.3.7.5.1.1.1.5 Layer 2 Timer Value Calculation
                6. 12.3.7.5.1.1.1.6 DL_FC0ProtectionTimeOutVal
                7. 12.3.7.5.1.1.1.7 DL_TC0ReplayTimeOutVal and DL_AFC0ReqTimeOut
              2. 12.3.7.5.1.1.2 UniPro CPort Connection Management
            2. 12.3.7.5.1.2 UFS Host Controller Initialization
            3. 12.3.7.5.1.3 HCE Bit
          2. 12.3.7.5.2 UFS Host Controller Programming
            1. 12.3.7.5.2.1 UFS Software Model
              1. 12.3.7.5.2.1.1 UFS Layers
              2. 12.3.7.5.2.1.2 UFS Protocol Elements
                1. 12.3.7.5.2.1.2.1 UPIU Types
                2. 12.3.7.5.2.1.2.2 UFS Protocol
              3. 12.3.7.5.2.1.3 UFS Host Data Structure
            2. 12.3.7.5.2.2 UFS Theory Of Operation
              1. 12.3.7.5.2.2.1 Building A UTP Transfer Request
              2. 12.3.7.5.2.2.2 Processing UTP Task Management Request Completion
              3. 12.3.7.5.2.2.3 Building UTP Task Management Request
              4. 12.3.7.5.2.2.4 Processing UTP Transfer Request Completion
              5. 12.3.7.5.2.2.5 UFS Host Processing
              6. 12.3.7.5.2.2.6 UFS Response Management Аnd Command Completion
          3. 12.3.7.5.3 UFS PHY Programming
          4. 12.3.7.5.4 UFS Hibernate Timings Considerations
    4. 12.4  Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 3356
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.2.4.2.3 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.2.4.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.2.4.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 3391
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3406
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3466
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
    5. 12.5  Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
      2. 12.5.2 Multichannel Audio Serial Port (MCASP)
        1. 12.5.2.1 MCASP Overview
          1. 12.5.2.1.1 MCASP Features
          2. 12.5.2.1.2 MCASP Not Supported Features
        2. 12.5.2.2 MCASP Environment
          1. 12.5.2.2.1 MCASP Signals
          2. 12.5.2.2.2 MCASP Protocols and Data Formats
            1. 12.5.2.2.2.1 Protocols Supported
            2. 12.5.2.2.2.2 Definition of Terms
            3. 12.5.2.2.2.3 TDM Format
            4. 12.5.2.2.2.4 I2S Format
            5. 12.5.2.2.2.5 S/PDIF Coding Format
              1. 12.5.2.2.2.5.1 Biphase-Mark Code
              2. 12.5.2.2.2.5.2 S/PDIF Subframe Format
              3. 12.5.2.2.2.5.3 Frame Format
        3. 12.5.2.3 MCASP Integration
          1. 12.5.2.3.1 MCASP Integration in MAIN Domain
        4. 12.5.2.4 MCASP Functional Description
          1. 12.5.2.4.1  MCASP Block Diagram
          2. 12.5.2.4.2  MCASP Clock and Frame-Sync Configurations
            1. 12.5.2.4.2.1 MCASP Transmit Clock
            2. 12.5.2.4.2.2 MCASP Receive Clock
            3. 12.5.2.4.2.3 Frame-Sync Generator
            4. 12.5.2.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations
          3. 12.5.2.4.3  MCASP Frame Sync Feedback for Cross Synchronization
          4. 12.5.2.4.4  MCASP Serializers
          5. 12.5.2.4.5  MCASP Format Units
            1. 12.5.2.4.5.1 Transmit Format Unit
              1. 12.5.2.4.5.1.1 TDM Mode Transmission Data Alignment Settings
              2. 12.5.2.4.5.1.2 DIT Mode Transmission Data Alignment Settings
            2. 12.5.2.4.5.2 Receive Format Unit
              1. 12.5.2.4.5.2.1 TDM Mode Reception Data Alignment Settings
          6. 12.5.2.4.6  MCASP State-Machines
          7. 12.5.2.4.7  MCASP TDM Sequencers
          8. 12.5.2.4.8  MCASP Software Reset
          9. 12.5.2.4.9  MCASP Power Management
          10. 12.5.2.4.10 MCASP Transfer Modes
            1. 12.5.2.4.10.1 Burst Transfer Mode
            2. 12.5.2.4.10.2 Time-Division Multiplexed (TDM) Transfer Mode
              1. 12.5.2.4.10.2.1 TDM Time Slots Generation and Processing
              2. 12.5.2.4.10.2.2 Special 384-Slot TDM Mode for Connection to External DIR
            3. 12.5.2.4.10.3 DIT Transfer Mode
              1. 12.5.2.4.10.3.1 Transmit DIT Encoding
              2. 12.5.2.4.10.3.2 Transmit DIT Clock and Frame-Sync Generation
              3. 12.5.2.4.10.3.3 DIT Channel Status and User Data Register Files
          11. 12.5.2.4.11 MCASP Data Transmission and Reception
            1. 12.5.2.4.11.1 Data Ready Status and Event/Interrupt Generation
              1. 12.5.2.4.11.1.1 Transmit Data Ready
              2. 12.5.2.4.11.1.2 Receive Data Ready
              3. 12.5.2.4.11.1.3 Transfers Through the Data Port (DATA)
              4. 12.5.2.4.11.1.4 Transfers Through the Configuration Bus (CFG)
              5. 12.5.2.4.11.1.5 Using a Device CPU for MCASP Servicing
              6. 12.5.2.4.11.1.6 Using the DMA for MCASP Servicing
          12. 12.5.2.4.12 MCASP Audio FIFO (AFIFO)
            1. 12.5.2.4.12.1 AFIFO Data Transmission
              1. 12.5.2.4.12.1.1 Transmit DMA Event Pacer
            2. 12.5.2.4.12.2 AFIFO Data Reception
              1. 12.5.2.4.12.2.1 Receive DMA Event Pacer
            3. 12.5.2.4.12.3 Arbitration Between Transmit and Receive DMA Requests
          13. 12.5.2.4.13 MCASP Events and Interrupt Requests
            1. 12.5.2.4.13.1 Transmit Data Ready Event and Interrupt
            2. 12.5.2.4.13.2 Receive Data Ready Event and Interrupt
            3. 12.5.2.4.13.3 Error Interrupt
            4. 12.5.2.4.13.4 Multiple Interrupts
          14. 12.5.2.4.14 MCASP DMA Requests
          15. 12.5.2.4.15 MCASP Loopback Modes
            1. 12.5.2.4.15.1 Loopback Mode Configurations
          16. 12.5.2.4.16 MCASP Error Reporting
            1. 12.5.2.4.16.1 Buffer Underrun Error -Transmitter
            2. 12.5.2.4.16.2 Buffer Overrun Error-Receiver
            3. 12.5.2.4.16.3 DATA Port Error - Transmitter
            4. 12.5.2.4.16.4 DATA Port Error - Receiver
            5. 12.5.2.4.16.5 Unexpected Frame Sync Error
            6. 12.5.2.4.16.6 Clock Failure Detection
              1. 12.5.2.4.16.6.1 Clock Failure Check Startup
              2. 12.5.2.4.16.6.2 Transmit Clock Failure Check and Recovery
              3. 12.5.2.4.16.6.3 Receive Clock Failure Check and Recovery
        5. 12.5.2.5 MCASP Programming Guide
          1. 12.5.2.5.1 MCASP Global Initialization
            1. 12.5.2.5.1.1 Surrounding Modules Global Initialization
            2. 12.5.2.5.1.2 MCASP Global Initialization
              1. 12.5.2.5.1.2.1 Main Sequence – MCASP Global Initialization for DIT-Transmission
                1. 12.5.2.5.1.2.1.1 Subsequence – Transmit Format Unit Configuration for DIT-Transmission
                2. 12.5.2.5.1.2.1.2 Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
                3. 12.5.2.5.1.2.1.3 Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
                4. 12.5.2.5.1.2.1.4 Subsequence - MCASP Pins Functional Configuration
                5. 12.5.2.5.1.2.1.5 Subsequence – DIT-specific Subframe Fields Configuration
              2. 12.5.2.5.1.2.2 Main Sequence – MCASP Global Initialization for TDM-Reception
                1. 12.5.2.5.1.2.2.1 Subsequence – Receive Format Unit Configuration in TDM Mode
                2. 12.5.2.5.1.2.2.2 Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
                3. 12.5.2.5.1.2.2.3 Subsequence – Receive Clock Generator Configuration
                4. 12.5.2.5.1.2.2.4 Subsequence—MCASP Receiver Pins Functional Configuration
              3. 12.5.2.5.1.2.3 Main Sequence – MCASP Global Initialization for TDM -Transmission
                1. 12.5.2.5.1.2.3.1 Subsequence – Transmit Format Unit Configuration in TDM Mode
                2. 12.5.2.5.1.2.3.2 Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
                3. 12.5.2.5.1.2.3.3 Subsequence – Transmit Clock Generator Configuration for TDM Cases
                4. 12.5.2.5.1.2.3.4 Subsequence—MCASP Transmit Pins Functional Configuration
          2. 12.5.2.5.2 MCASP Operational Modes Configuration
            1. 12.5.2.5.2.1 MCASP Transmission Modes
              1. 12.5.2.5.2.1.1 Main Sequence – MCASP DIT- /TDM- Polling Transmission Method
              2. 12.5.2.5.2.1.2 Main Sequence – MCASP DIT- /TDM - Interrupt Transmission Method
              3. 12.5.2.5.2.1.3 Main Sequence –MCASP DIT- /TDM - Mode DMA Transmission Method
            2. 12.5.2.5.2.2 MCASP Reception Modes
              1. 12.5.2.5.2.2.1 Main Sequence – MCASP Polling Reception Method
              2. 12.5.2.5.2.2.2 Main Sequence – MCASP TDM - Interrupt Reception Method
              3. 12.5.2.5.2.2.3 Main Sequence – MCASP TDM - Mode DMA Reception Method
            3. 12.5.2.5.2.3 MCASP Event Servicing
              1. 12.5.2.5.2.3.1 MCASP DIT-/TDM- Transmit Interrupt Events Servicing
              2. 12.5.2.5.2.3.2 MCASP TDM- Receive Interrupt Events Servicing
              3. 12.5.2.5.2.3.3 Subsequence – MCASP DIT-/TDM -Modes Transmit Error Handling
              4. 12.5.2.5.2.3.4 Subsequence – MCASP Receive Error Handling
    6. 12.6  Display Subsystem (DSS) and Peripherals
      1. 12.6.1 DSS Overview
        1. 12.6.1.1 DSS Features
        2. 12.6.1.2 DSS Not Supported Features
      2. 12.6.2 DSS Environment
        1. 12.6.2.1 DISPC Environment
          1. 12.6.2.1.1 RGB Data Output
          2. 12.6.2.1.2 YUV Data Output (BT.656/BT.1120)
          3. 12.6.2.1.3 Display Timing Diagrams
          4. 12.6.2.1.4 VSYNC/HSYNC/DE Signal Export to SoC Boundary
        2. 12.6.2.2 DSI Environment
        3. 12.6.2.3 EDP Environment
      3. 12.6.3 DSS Integration
        1. 12.6.3.1 DISPC Integration
        2. 12.6.3.2 DSI Integration
        3. 12.6.3.3 EDP Integration
      4. 12.6.4 Display Subsystem Controller (DISPC) with Frame Buffer Decompression Core (FBDC)
        1. 12.6.4.1  DISPC Overview
        2. 12.6.4.2  DISPC Clocks
        3. 12.6.4.3  DISPC Resets
        4. 12.6.4.4  DISPC Power Management
        5. 12.6.4.5  DISPC Interrupt Requests
        6. 12.6.4.6  DISPC DMA Controller
          1. 12.6.4.6.1  DISPC DMA Addressing and Bursts
          2. 12.6.4.6.2  DISPC Read DMA Buffers
          3. 12.6.4.6.3  DISPC Write DMA Buffer
          4. 12.6.4.6.4  DISPC Flip/Mirror Support
          5. 12.6.4.6.5  DISPC DMA Predecimation
          6. 12.6.4.6.6  DISPC DMA Buffer Sharing
          7. 12.6.4.6.7  DISPC DMA MFLAG Mechanism
          8. 12.6.4.6.8  DISPC DMA Priority Requests Control
          9. 12.6.4.6.9  DISPC DMA Arbitration
          10. 12.6.4.6.10 DISPC DMA Ultra-Low Power Mode
          11. 12.6.4.6.11 DISPC Compressed Data Format Support
            1. 12.6.4.6.11.1 FBDC Tile Request
            2. 12.6.4.6.11.2 FBDC Source Cropping
        7. 12.6.4.7  DISPC Pixel Data Formats
        8. 12.6.4.8  DISPC Video Pipeline
          1. 12.6.4.8.1 DISPC VID Replication Logic
          2. 12.6.4.8.2 DISPC VID VC-1 Range Mapping Unit
          3. 12.6.4.8.3 DISPC VID Color Look-Up Table (CLUT)
          4. 12.6.4.8.4 DISPC VID Chrominance Resampling
            1. 12.6.4.8.4.1 Chrominance Resampling for VID Pipeline
            2. 12.6.4.8.4.2 Chrominance Resampling for VIDL Pipeline
          5. 12.6.4.8.5 DISPC VID Scaler Unit
          6. 12.6.4.8.6 DISPC VID Color Space Conversion YUV to RGB
          7. 12.6.4.8.7 DISPC VID Brightness/Contrast/Saturation/Hue Control
          8. 12.6.4.8.8 DISPC VID Luma Key Support
          9. 12.6.4.8.9 DISPC VID Cropping Support
        9. 12.6.4.9  DISPC Write-Back Pipeline
          1. 12.6.4.9.1 DISPC WB Color Space Conversion RGB to YUV
          2. 12.6.4.9.2 DISPC WB Scaler Unit
        10. 12.6.4.10 DISPC Overlay Manager
          1. 12.6.4.10.1 DISPC Overlay Input Selector
          2. 12.6.4.10.2 DISPC Overlay Mechanism
            1. 12.6.4.10.2.1 Overlay Alpha Blender
            2. 12.6.4.10.2.2 Overlay Transparency Color Keys
          3. 12.6.4.10.3 Overlay 3D Support
          4. 12.6.4.10.4 Overlay Color Bar Insertion
        11. 12.6.4.11 DISPC Video Port Output
          1. 12.6.4.11.1  DISPC VP Gamma Correction Unit
          2. 12.6.4.11.2  DISPC VP Color Phase Rotation Unit
          3. 12.6.4.11.3  DISPC VP Color Space Conversion - RGB to YUV
          4. 12.6.4.11.4  DISPC VP BT.656 and BT.1120 Modes
            1. 12.6.4.11.4.1 DISPC BT Mode Blanking
            2. 12.6.4.11.4.2 DISPC BT Mode EAV and SAV
          5. 12.6.4.11.5  DISPC VP Spatial/Temporal Dithering
          6. 12.6.4.11.6  DISPC VP Multiple Cycle Output Format (TDM)
          7. 12.6.4.11.7  DISPC VP Stall Mode
          8. 12.6.4.11.8  DISPC VP Timing Generator and Display Panel Settings
          9. 12.6.4.11.9  DISPC VP Merge-Split-Sync (MSS) Module
            1. 12.6.4.11.9.1 MSS Clocking Scheme
            2. 12.6.4.11.9.2 MSS Merge with Scaling
          10. 12.6.4.11.10 DISPC Internal Diagnostic Features
            1. 12.6.4.11.10.1 Internal Diagnostic Check Regions
            2. 12.6.4.11.10.2 Internal Diagnostic Signature Generator Using MISR
            3. 12.6.4.11.10.3 Internal Diagnostic Checks
            4. 12.6.4.11.10.4 Internal Diagnostic Check Limitations
          11. 12.6.4.11.11 DISPC Security Management
            1. 12.6.4.11.11.1 Security Implementation
            2. 12.6.4.11.11.2 Secure Mode Configuration
          12. 12.6.4.11.12 DISPC Shadow Mechanism for Registers
          13. 12.6.4.11.13 DISPC Registers
            1. 12.6.4.11.13.1 DSS_COMMON Registers
            2. 12.6.4.11.13.2 DSS_VID Registers
            3. 12.6.4.11.13.3 DSS_OVR Registers
            4. 12.6.4.11.13.4 DSS_VP Registers
            5. 12.6.4.11.13.5 DSS_WB Registers
      5. 12.6.5 MIPI Display Serial Interface (DSI) Controller
        1. 12.6.5.1 DSI Block Diagram
        2. 12.6.5.2 DSI Clocking
        3. 12.6.5.3 DSI Reset
        4. 12.6.5.4 DSI Power Management
        5. 12.6.5.5 DSI Interrupts
        6. 12.6.5.6 DSI Internal Interfaces
          1. 12.6.5.6.1 Video Input Interfaces
            1. 12.6.5.6.1.1 Pixel Mapping
          2. 12.6.5.6.2 DPI (Pixel Stream Interface)
            1. 12.6.5.6.2.1 Signals
          3. 12.6.5.6.3 SDI (Serial Data Interface)
            1. 12.6.5.6.3.1 Secure Display Support
        7. 12.6.5.7 DSI Programming Guide
          1. 12.6.5.7.1  Application Guidelines
            1. 12.6.5.7.1.1 Overview of a Display Subsystem
            2. 12.6.5.7.1.2 D-PHY And DSI Configuration
            3. 12.6.5.7.1.3 DSI Controller Initialization
            4. 12.6.5.7.1.4 Panel Configuration Using Command Mode
            5. 12.6.5.7.1.5 VIDEO Interface Configuration
          2. 12.6.5.7.2  Application Considerations
            1. 12.6.5.7.2.1 D-PHY Timings Control
            2. 12.6.5.7.2.2 Control Block
            3. 12.6.5.7.2.3 Video Coherency
          3. 12.6.5.7.3  Start-up Procedure
          4. 12.6.5.7.4  Interrupt Management
            1. 12.6.5.7.4.1 Error and Status Registers
            2. 12.6.5.7.4.2 Interrupt Management for Direct Command Registers
          5. 12.6.5.7.5  Direct Command Usage
            1. 12.6.5.7.5.1 Trigger Mapping Information
            2. 12.6.5.7.5.2 Command Mode Settings
            3. 12.6.5.7.5.3 Bus Turnaround Sequence
            4. 12.6.5.7.5.4 Tearing Effect Control
            5. 12.6.5.7.5.5 Tearing Effect Control on Panels with Frame Buffer
            6. 12.6.5.7.5.6 Return Path Operation
            7. 12.6.5.7.5.7 EoT Packet Management
            8. 12.6.5.7.5.8 ECC Correction
            9. 12.6.5.7.5.9 LP Transmission and BTA
          6. 12.6.5.7.6  Low-power Management
          7. 12.6.5.7.7  Video Mode Settings
            1. 12.6.5.7.7.1 Video Stream Presentation
            2. 12.6.5.7.7.2 Video Stream Settings (VSG)
            3. 12.6.5.7.7.3 VCA Configuration
            4. 12.6.5.7.7.4 TVG Configuration
          8. 12.6.5.7.8  DPI To DSI Programming
            1. 12.6.5.7.8.1 DSI and DPHY Operation
            2. 12.6.5.7.8.2 Pixel Clock to TX_BYTE_CLK Variation
            3. 12.6.5.7.8.3 LP Operation
            4. 12.6.5.7.8.4 DPI Interface Burst Operation
          9. 12.6.5.7.9  Programming the DSITX Controller to Match the Incoming DPI Stream
            1. 12.6.5.7.9.1 Vertical Timing
            2. 12.6.5.7.9.2 Horizontal Timing for Non-Burst Mode with Sync Pulses
            3. 12.6.5.7.9.3 Event Mode Horizontal Timing
            4. 12.6.5.7.9.4 Burst Event Mode Horizontal Timing
            5. 12.6.5.7.9.5 Burst Mode Operation
            6. 12.6.5.7.9.6 Example Configurations
            7. 12.6.5.7.9.7 Stereoscopic Video Support
          10. 12.6.5.7.10 DSITX Video Stream Variable Refresh
      6. 12.6.6 Embedded DisplayPort (еDP) Transmitter
        1. 12.6.6.1 EDP Block Diagram
        2. 12.6.6.2 EDP Wrapper Functions
          1. 12.6.6.2.1 Video Stream Clock/Data Muxing
          2. 12.6.6.2.2 Secure Video Content Protection
          3. 12.6.6.2.3 DPI_DATA Input Pixel Format Supported
          4. 12.6.6.2.4 Audio Input Interface
            1. 12.6.6.2.4.1 Audio I2S Signals/Timing
            2. 12.6.6.2.4.2 Audio I2S Clock Frequency
        3. 12.6.6.3 EDP Transmitter Controller Subsystem (MHDPTX_TOP)
          1. 12.6.6.3.1 Display Stream Compression Encoder (DSC)
            1. 12.6.6.3.1.1 DSC Encoder Features
            2. 12.6.6.3.1.2 Usage Models for EDP
          2. 12.6.6.3.2 Display Port Transmitter Controller (MHDPTX Controller)
            1. 12.6.6.3.2.1 EDP Transmitter Controller Mode Configurations
        4. 12.6.6.4 EDP AUX_PHY Interface
        5. 12.6.6.5 EDP Clocks
          1. 12.6.6.5.1 Clock Diagram
            1. 12.6.6.5.1.1 DPI Interface Clock Sourcing
            2. 12.6.6.5.1.2 Memory Clock Gating
            3. 12.6.6.5.1.3 PHY Clock Connections
          2. 12.6.6.5.2 Clock Groups
        6. 12.6.6.6 EDP Resets
        7. 12.6.6.7 EDP Interrupt Requests
          1. 12.6.6.7.1 EDP_INTR Interrupt Description
          2. 12.6.6.7.2 EDP_INTR_ASF Interrupt Description
        8. 12.6.6.8 EDP Embedded Memories
          1. 12.6.6.8.1 MHDPTX Controller Memories
          2. 12.6.6.8.2 DSC Memories
          3. 12.6.6.8.3 ECC Aggregation
        9. 12.6.6.9 EDP Programmer's Guide
          1. 12.6.6.9.1 EDP Controller Programming
            1. 12.6.6.9.1.1  MHDPTX Register/Memory Regions
            2. 12.6.6.9.1.2  Boot Sequence
            3. 12.6.6.9.1.3  Setting Core Clock Frequency
            4. 12.6.6.9.1.4  Loading Firmware
            5. 12.6.6.9.1.5  FW Running indication
            6. 12.6.6.9.1.6  Software Events Handling
            7. 12.6.6.9.1.7  DisplayPort Source (TX) Sequence
            8. 12.6.6.9.1.8  HDCP
              1. 12.6.6.9.1.8.1 Embedded HDCP Crypto
              2. 12.6.6.9.1.8.2 Additional Security Features
                1. 12.6.6.9.1.8.2.1 KM-Key Encryption
                2. 12.6.6.9.1.8.2.2 Cyphertext Stealing
            9. 12.6.6.9.1.9  HD Display TX Controller
              1. 12.6.6.9.1.9.1 Info-Frame Handling
                1. 12.6.6.9.1.9.1.1 EDID Handling
                2. 12.6.6.9.1.9.1.2 Audio Control
                3. 12.6.6.9.1.9.1.3 Video Control
            10. 12.6.6.9.1.10 DPTX TX Controller
              1. 12.6.6.9.1.10.1 Protocol over Auxiliary
              2. 12.6.6.9.1.10.2 PHY (Physical layer) Handling
          2. 12.6.6.9.2 EDP PHY Wrapper Initialization
          3. 12.6.6.9.3 EDP PHY Programming
    7. 12.7  Camera Subsystem
      1. 12.7.1 Camera Streaming Interface Receiver (CSI_RX_IF)
        1. 12.7.1.1 CSI_RX_IF Overview
          1. 12.7.1.1.1 CSI_RX_IF Features
          2. 12.7.1.1.2 CSI_RX_IF Not Supported Features
        2. 12.7.1.2 CSI_RX_IF Environment
        3. 12.7.1.3 CSI_RX_IF Integration
          1. 12.7.1.3.1 CSI_RX_IF Integration in MAIN Domain
        4. 12.7.1.4 CSI_RX_IF Functional Description
          1. 12.7.1.4.1 CSI_RX_IF Block Diagram
          2. 12.7.1.4.2 CSI_RX_IF Hardware and Software Reset
          3. 12.7.1.4.3 CSI_RX_IF Clock Configuration
          4. 12.7.1.4.4 CSI_RX_IF Interrupt Events
          5. 12.7.1.4.5 CSI_RX_IF Data Memory Organization Details
          6. 12.7.1.4.6 CSI_RX_IF PSI_L (DMA) Interface
            1. 12.7.1.4.6.1 PSI_L DMA framing
            2. 12.7.1.4.6.2 PSI_L DMA error handling due to FIFO overflow
          7. 12.7.1.4.7 CSI_RX_IF ECC Protection Support
          8. 12.7.1.4.8 CSI_RX_IF Programming Guide
            1. 12.7.1.4.8.1  Overview
            2. 12.7.1.4.8.2  Controller Configuration
            3. 12.7.1.4.8.3  Power on Configuration
            4. 12.7.1.4.8.4  Stream Start and Stop
            5. 12.7.1.4.8.5  Error Control With Soft Resets
            6. 12.7.1.4.8.6  Stream Error Detected – No Error Bypass Mode
            7. 12.7.1.4.8.7  Stream Error Detected – Error Bypass Mode
            8. 12.7.1.4.8.8  Stream Error Detected – Soft Reset Recovery
            9. 12.7.1.4.8.9  Stream Monitor Configuration
            10. 12.7.1.4.8.10 Stream Monitor Frame Capture Control
            11. 12.7.1.4.8.11 Stream Monitor Timer interrupt
            12. 12.7.1.4.8.12 Stream Monitor Line/Byte Counters Interrupt
            13. 12.7.1.4.8.13 Example Controller Programming Sequence (Single Stream Operation)
            14. 12.7.1.4.8.14 CSI_RX_IF Programming Restrictions
            15. 12.7.1.4.8.15 CSI_RX_IF Real-time operating requirements
      2. 12.7.2 MIPI D-PHY Receiver (DPHY_RX)
        1. 12.7.2.1 DPHY_RX Overview
          1. 12.7.2.1.1 DPHY_RX Features
          2. 12.7.2.1.2 DPHY_RX Not Supported Features
        2. 12.7.2.2 DPHY_RX Environment
        3. 12.7.2.3 DPHY_RX Integration
          1. 12.7.2.3.1 DPHY_RX Integration in MAIN Domain
        4. 12.7.2.4 DPHY_RX Functional Description
          1. 12.7.2.4.1 DPHY_RX Programming Guide
            1. 12.7.2.4.1.1 Overview
            2. 12.7.2.4.1.2 Initial Configuration Programming
              1. 12.7.2.4.1.2.1 Start-up Sequence Timing Diagram
            3. 12.7.2.4.1.3 Common Configuration
            4. 12.7.2.4.1.4 Lane Configuration
            5. 12.7.2.4.1.5 Procedure: Clock Lane Low Power Analog Receiver Functions Test
              1. 12.7.2.4.1.5.1 Description of Procedure
              2. 12.7.2.4.1.5.2 Details of the Procedure
            6. 12.7.2.4.1.6 Procedure: Data Lane Low Power Analog Receiver Functions Test
              1. 12.7.2.4.1.6.1 Description of Procedure
              2. 12.7.2.4.1.6.2 Details of the Procedure
            7. 12.7.2.4.1.7 Procedure: Clock and Data Lane High Speed Receiver BIST Functions Test
              1. 12.7.2.4.1.7.1 Description of Procedure
              2. 12.7.2.4.1.7.2 Details of the Procedure
      3. 12.7.3 Camera Streaming Interface Transmitter (CSI_TX_IF)
        1. 12.7.3.1 CSI_TX_IF Overview
          1. 12.7.3.1.1 CSI_TX_IF Features
          2. 12.7.3.1.2 CSI_TX_IF Not Supported Features
        2. 12.7.3.2 CSI_TX_IF Environment
        3. 12.7.3.3 CSI_TX_IF Integration
          1. 12.7.3.3.1 CSI_TX_IF Integration in MAIN Domain
        4. 12.7.3.4 CSI_TX_IF Functional Description
          1. 12.7.3.4.1 CSI_TX_IF Block Diagram
          2. 12.7.3.4.2 CSI_TX_IF Hardware and Software Reset
          3. 12.7.3.4.3 CSI_TX_IF Clock Configuration
          4. 12.7.3.4.4 CSI_TX_IF Interrupt Events
          5. 12.7.3.4.5 CSI_TX_IF Data Memory Organization Details
          6. 12.7.3.4.6 CSI_TX_IF PSI_L (DMA) Interface
          7. 12.7.3.4.7 CSI_TX_IF ECC Protection Support
        5. 12.7.3.5 CSI_TX_IF Programming Guide
          1. 12.7.3.5.1  Programming (Configuration Mode)
          2. 12.7.3.5.2  System Initialization Programming
          3. 12.7.3.5.3  Lane Control Programming
          4. 12.7.3.5.4  Line Control
          5. 12.7.3.5.5  Line Control Arbitration
          6. 12.7.3.5.6  Lane Manager FSM
          7. 12.7.3.5.7  Data Lane Control FSM
          8. 12.7.3.5.8  Clock Lane Control
          9. 12.7.3.5.9  Clock Lane Control FSMs
          10. 12.7.3.5.10 CSI_TX_IF Configuration for PSI_L
          11. 12.7.3.5.11 CSI_TX_IF Configuration for Re-transmit
          12. 12.7.3.5.12 CSI_TX_IF Configuration for Color Bar
          13. 12.7.3.5.13 CSI_TX_IF Error Recovery
          14. 12.7.3.5.14 CSI_TX_IF Power Up/Down Sequence
    8. 12.8  Shared MIPI D-PHY Transmitter (DPHY_TX)
      1. 12.8.1 DPHY_TX Subsystem Overview
        1. 12.8.1.1 DPHY_TX Features
      2. 12.8.2 DPHY_TX Environment
      3. 12.8.3 DPHY_TX Integration
    9. 12.9  Video Processing Front End (VPFE)
      1. 12.9.1 VPFE Overview
        1. 12.9.1.1 VPFE Features
        2. 12.9.1.2 VPFE Not Supported Features
      2. 12.9.2 VPFE Environment
        1. 12.9.2.1 VPFE External System Interface
      3. 12.9.3 VPFE Integration
        1. 12.9.3.1 VPFE Integration in MAIN Domain
      4. 12.9.4 VPFE Functional Description
        1. 12.9.4.1 VPFE Block Diagram
          1. 12.9.4.1.1 CCD Controller (CCDC)
          2. 12.9.4.1.2 Shared Buffer Logic (SBL)
          3. 12.9.4.1.3 Region-based Address Translation
        2. 12.9.4.2 VPFE Power Management
        3. 12.9.4.3 VPFE Interrupts
        4. 12.9.4.4 VPFE Register Configuration
          1. 12.9.4.4.1 General Register Setup
          2. 12.9.4.4.2 Status
          3. 12.9.4.4.3 CCDC_VD Latched Registers
            1. 12.9.4.4.3.1 Inter-Frame Operations
        5. 12.9.4.5 VPFE Limitations
        6. 12.9.4.6 VPFE Interfaces
          1. 12.9.4.6.1 Interfaces Summary
          2. 12.9.4.6.2 Timing Generator and Frame Settings
          3. 12.9.4.6.3 ITU-R BT.656 Interface
          4. 12.9.4.6.4 Digital YCbCr Interface
        7. 12.9.4.7 VPFE Data / Image Processing
          1. 12.9.4.7.1 Raw Data Mode
            1. 12.9.4.7.1.1 Input Sampling and Formatting for Raw Data Mode
            2. 12.9.4.7.1.2 Optical Black Clamping for Raw Data Mode
            3. 12.9.4.7.1.3 Black Level Compensation
            4. 12.9.4.7.1.4 Output Formatter for Raw Data Mode
              1. 12.9.4.7.1.4.1 Low Pass Filter (LPF)
              2. 12.9.4.7.1.4.2 Culling
              3. 12.9.4.7.1.4.3 A-Law Transformation
              4. 12.9.4.7.1.4.4 Line Output Control
              5. 12.9.4.7.1.4.5 Output Format in External Memory for Raw Data Mode
          2. 12.9.4.7.2 YCbCr and BT.656 Modes
            1. 12.9.4.7.2.1 Input Sampling and Formatting for YCbCr and BT.656 Modes
            2. 12.9.4.7.2.2 Black Clamping for YCbCr and BT.656 Modes
            3. 12.9.4.7.2.3 Output Formatter for YCbCr and BT.656 Modes
              1. 12.9.4.7.2.3.1 Output Format in External Memory for YCbCr and BT.656 Modes
    10. 12.10 Timer Modules
      1. 12.10.1 Global Timebase Counter (GTC)
        1. 12.10.1.1 GTC Overview
          1. 12.10.1.1.1 GTC Features
          2. 12.10.1.1.2 GTC Not Supported Features
        2. 12.10.1.2 GTC Integration
        3. 12.10.1.3 GTC Functional Description
          1. 12.10.1.3.1 GTC Block Diagram
          2. 12.10.1.3.2 GTC Counter
          3. 12.10.1.3.3 GTC Gray Encoder
          4. 12.10.1.3.4 GTC Push Event Generation
          5. 12.10.1.3.5 GTC Register Partitioning
      2. 12.10.2 Windowed Watchdog Timer (WWDT)
        1. 12.10.2.1 RTI Overview
          1. 12.10.2.1.1 RTI Features
          2. 12.10.2.1.2 RTI Not Supported Features
        2. 12.10.2.2 RTI Integration
          1. 12.10.2.2.1 RTI Integration in MCU Domain
          2. 12.10.2.2.2 RTI Integration in MAIN Domain
        3. 12.10.2.3 RTI Functional Description
          1. 12.10.2.3.1 RTI Counter Operation
          2. 12.10.2.3.2 RTI Digital Watchdog
          3. 12.10.2.3.3 RTI Digital Windowed Watchdog
          4. 12.10.2.3.4 RTI Low Power Mode Operation
          5. 12.10.2.3.5 RTI Debug Mode Behavior
      3. 12.10.3 Timers
        1. 12.10.3.1 Timers Overview
          1. 12.10.3.1.1 Timers Features
          2. 12.10.3.1.2 Timers Not Supported Features
        2. 12.10.3.2 Timers Environment
          1. 12.10.3.2.1 Timer External System Interface
        3. 12.10.3.3 Timers Integration
          1. 12.10.3.3.1 Timers Integration in MCU Domain
          2. 12.10.3.3.2 Timers Integration in MAIN Domain
        4. 12.10.3.4 Timers Functional Description
          1. 12.10.3.4.1  Timer Block Diagram
          2. 12.10.3.4.2  Timer Power Management
            1. 12.10.3.4.2.1 Wake-Up Capability
          3. 12.10.3.4.3  Timer Software Reset
          4. 12.10.3.4.4  Timer Interrupts
          5. 12.10.3.4.5  Timer Mode Functionality
            1. 12.10.3.4.5.1 1-ms Tick Generation
          6. 12.10.3.4.6  Timer Capture Mode Functionality
          7. 12.10.3.4.7  Timer Compare Mode Functionality
          8. 12.10.3.4.8  Timer Prescaler Functionality
          9. 12.10.3.4.9  Timer Pulse-Width Modulation
          10. 12.10.3.4.10 Timer Counting Rate
          11. 12.10.3.4.11 Timer Under Emulation
          12. 12.10.3.4.12 Accessing Timer Registers
            1. 12.10.3.4.12.1 Writing to Timer Registers
              1. 12.10.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.10.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.10.3.4.12.2 Reading From Timer Counter Registers
              1. 12.10.3.4.12.2.1 Read Posted
              2. 12.10.3.4.12.2.2 Read Non-Posted
          13. 12.10.3.4.13 Timer Posted Mode Selection
        5. 12.10.3.5 Timers Low-Level Programming Models
          1. 12.10.3.5.1 Timer Global Initialization
            1. 12.10.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.10.3.5.1.2 Timer Module Global Initialization
              1. 12.10.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.10.3.5.2 Timer Operational Mode Configuration
            1. 12.10.3.5.2.1 Timer Mode
              1. 12.10.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.10.3.5.2.2 Timer Compare Mode
              1. 12.10.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.10.3.5.2.3 Timer Capture Mode
              1. 12.10.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.10.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.10.3.5.2.3.3 Subsequence – Detect Event
            4. 12.10.3.5.2.4 Timer PWM Mode
              1. 12.10.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
    11. 12.11 Internal Diagnostics Modules
      1. 12.11.1 Dual Clock Comparator (DCC)
        1. 12.11.1.1 DCC Overview
          1. 12.11.1.1.1 DCC Features
          2. 12.11.1.1.2 DCC Not Supported Features
        2. 12.11.1.2 DCC Integration
          1. 12.11.1.2.1 DCC Integration in MCU Domain
          2. 12.11.1.2.2 DCC Integration in MAIN Domain
        3. 12.11.1.3 DCC Functional Description
          1. 12.11.1.3.1 DCC Counter Operation
          2. 12.11.1.3.2 DCC Low Power Mode Operation
          3. 12.11.1.3.3 DCC Suspend Mode Behavior
          4. 12.11.1.3.4 DCC Single-Shot Mode
          5. 12.11.1.3.5 DCC Continuous mode
            1. 12.11.1.3.5.1 DCC Continue on Error
            2. 12.11.1.3.5.2 DCC Error Count
          6. 12.11.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.11.1.3.7 DCC Error Trajectory record
            1. 12.11.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.11.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.11.1.3.7.3 DCC FIFO Details
            4. 12.11.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.11.1.3.8 DCC Count read registers
        4. 12.11.1.4 DCC Registers
      2. 12.11.2 Error Signaling Module (ESM)
        1. 12.11.2.1 ESM Overview
          1. 12.11.2.1.1 ESM Features
        2. 12.11.2.2 ESM Environment
        3. 12.11.2.3 ESM Integration
          1. 12.11.2.3.1 ESM Integration in WKUP Domain
          2. 12.11.2.3.2 ESM Integration in MCU Domain
          3. 12.11.2.3.3 ESM Integration in MAIN Domain
        4. 12.11.2.4 ESM Functional Description
          1. 12.11.2.4.1 ESM Interrupt Requests
            1. 12.11.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.11.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.11.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.11.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.11.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.11.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.11.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.11.2.4.2 ESM Error Event Inputs
          3. 12.11.2.4.3 ESM Error Pin Output
          4. 12.11.2.4.4 ESM Minimum Time Interval
          5. 12.11.2.4.5 ESM Protection for Registers
          6. 12.11.2.4.6 ESM Clock Stop
      3. 12.11.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.11.3.1 MCRC Overview
          1. 12.11.3.1.1 MCRC Features
          2. 12.11.3.1.2 MCRC Not Supported Features
        2. 12.11.3.2 MCRC Integration
        3. 12.11.3.3 MCRC Functional Description
          1. 12.11.3.3.1  MCRC Block Diagram
          2. 12.11.3.3.2  MCRC General Operation
          3. 12.11.3.3.3  MCRC Modes of Operation
            1. 12.11.3.3.3.1 AUTO Mode
            2. 12.11.3.3.3.2 Semi-CPU Mode
            3. 12.11.3.3.3.3 Full-CPU Mode
          4. 12.11.3.3.4  PSA Signature Register
          5. 12.11.3.3.5  PSA Sector Signature Register
          6. 12.11.3.3.6  CRC Value Register
          7. 12.11.3.3.7  Raw Data Register
          8. 12.11.3.3.8  Example DMA Controller Setup
            1. 12.11.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.11.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.11.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.11.3.3.9  Pattern Count Register
          10. 12.11.3.3.10 Sector Count Register/Current Sector Register
          11. 12.11.3.3.11 Interrupts
            1. 12.11.3.3.11.1 Compression Complete Interrupt
            2. 12.11.3.3.11.2 CRC Fail Interrupt
            3. 12.11.3.3.11.3 Overrun Interrupt
            4. 12.11.3.3.11.4 Underrun Interrupt
            5. 12.11.3.3.11.5 Timeout Interrupt
            6. 12.11.3.3.11.6 Interrupt Offset Register
            7. 12.11.3.3.11.7 Error Handling
          12. 12.11.3.3.12 Power Down Mode
          13. 12.11.3.3.13 Emulation
        4. 12.11.3.4 MCRC Programming Examples
          1. 12.11.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.11.3.4.1.1 DMA Setup
            2. 12.11.3.4.1.2 Timer Setup
            3. 12.11.3.4.1.3 CRC Setup
          2. 12.11.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.11.3.4.2.1 DMA Setup
            2. 12.11.3.4.2.2 CRC Setup
          3. 12.11.3.4.3 Example: Semi-CPU Mode
            1. 12.11.3.4.3.1 DMA Setup
            2. 12.11.3.4.3.2 Timer Setup
            3. 12.11.3.4.3.3 CRC Setup
          4. 12.11.3.4.4 Example: Full-CPU Mode
            1. 12.11.3.4.4.1 CRC Setup
      4. 12.11.4 ECC Aggregator
        1. 12.11.4.1 ECC Aggregator Overview
          1. 12.11.4.1.1 ECC Aggregator Features
        2. 12.11.4.2 ECC Aggregator Integration
        3. 12.11.4.3 ECC Aggregator Functional Description
          1. 12.11.4.3.1 ECC Aggregator Block Diagram
          2. 12.11.4.3.2 ECC Aggregator Register Groups
          3. 12.11.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.11.4.3.4 Serial Write Operation
          5. 12.11.4.3.5 Interrupts
          6. 12.11.4.3.6 Inject Only Mode
  15. 13On-Chip Debug
    1. 13.1 Introduction to SoC Debug Framework
  16.   Revision History

2.1 MAIN Domain Memory Map

Table 2-1 shows the MAIN domain memory map.

Note:

The memory locations not shown in Table 2-1 are either unallocated or reserved and not used. Accesses to these locations are not recommended and should be avoided.

Table 2-1 MAIN Domain Memory Map
Region NameStart AddressEnd AddressSize
PSRAM2KECC0_RAM0x00000000000x00000007FF2 KB
CTRL_MMR0_CFG00x00001000000x000011FFFF128 KB
PSRAMECC0_RAM0x00002000000x00002003FF1 KB
EFUSE00x00003000000x00003000FF256 B
PSC00x00004000000x0000400FFF4 KB
PLLCTRL00x00004100000x00004101FF512 B
PBIST60x00004200000x00004203FF1 KB
DFTSS00x00005000000x00005003FF1 KB
GPIO00x00006000000x00006000FF256 B
GPIO10x00006010000x00006010FF256 B
GPIO20x00006100000x00006100FF256 B
GPIO30x00006110000x00006110FF256 B
GPIO40x00006200000x00006200FF256 B
GPIO50x00006210000x00006210FF256 B
GPIO60x00006300000x00006300FF256 B
GPIO70x00006310000x00006310FF256 B
PLL0_CFG0x00006800000x000069FFFF128 KB
ESM0_CFG0x00007000000x0000700FFF4 KB
PSRAM2KECC0_ECC_AGGR0x00007800000x00007803FF1 KB
PSRAMECC0_ECC_AGGR0x00007840000x00007843FF1 KB
DCC00x00008000000x000080003F64 B
DCC10x00008040000x000080403F64 B
DCC20x00008080000x000080803F64 B
DCC30x000080C0000x000080C03F64 B
DCC40x00008100000x000081003F64 B
DCC50x00008140000x000081403F64 B
DCC60x00008180000x000081803F64 B
DCC70x000081C0000x000081C03F64 B
DCC80x00008200000x000082003F64 B
DCC90x00008240000x000082403F64 B
DCC100x00008280000x000082803F64 B
DCC110x000082C0000x000082C03F64 B
DCC120x00008300000x000083003F64 B
GPIOMUX_INTRTR0_INTR_ROUTER_CFG0x0000A000000x0000A007FF2 KB
MAIN2MCU_LVL_INTRTR0_CFG0x0000A100000x0000A107FF2 KB
MAIN2MCU_PLS_INTRTR0_CFG0x0000A200000x0000A207FF2 KB
CMPEVENT_INTRTR0_INTR_ROUTER_CFG0x0000A300000x0000A303FF1 KB
TIMESYNC_INTRTR0_INTR_ROUTER_CFG0x0000A400000x0000A407FF2 KB
R5FSS0_INTROUTER0_INTR_ROUTER_CFG0x0000A600000x0000A61FFF8 KB
R5FSS1_INTROUTER0_INTR_ROUTER_CFG0x0000A700000x0000A71FFF8 KB
GTC0_GTC_CFG00x0000A800000x0000A803FF1 KB
GTC0_GTC_CFG10x0000A900000x0000A93FFF16 KB
GTC0_GTC_CFG20x0000AA00000x0000AA3FFF16 KB
GTC0_GTC_CFG30x0000AB00000x0000AB3FFF16 KB
C66SS0_INTROUTER0_INTR_ROUTER_CFG0x0000AC00000x0000AC0FFF4 KB
C66SS1_INTROUTER0_INTR_ROUTER_CFG0x0000AD00000x0000AD0FFF4 KB
CBASS_INFRA0_ERR0x0000B000000x0000B003FF1 KB
CBASS_FW0_ERR0x0000B080000x0000B083FF1 KB
ECC_AGGR0_ECC_AGGR0x0000C020000x0000C023FF1 KB
COMPUTE_CLUSTER0_GIC_TRANSLATER0x00010000000x00013FFFFF4 MB
COMPUTE_CLUSTER0_GIC_DISTRIBUTOR0x00018000000x000180FFFF64 KB
COMPUTE_CLUSTER0_GIC_MESSAGE_BASED_SPIS0x00018100000x000181FFFF64 KB
COMPUTE_CLUSTER0_GIC_ITS0x00018200000x000182FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_00x00019000000x000190FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_00x00019100000x000191FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_10x00019200000x000192FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_10x00019300000x000193FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_20x00019400000x000194FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_20x00019500000x000195FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_30x00019600000x000196FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_30x00019700000x000197FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_40x00019800000x000198FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_40x00019900000x000199FFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_50x00019A00000x00019AFFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_50x00019B00000x00019BFFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_60x00019C00000x00019CFFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_60x00019D00000x00019DFFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_70x00019E00000x00019EFFFF64 KB
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_70x00019F00000x00019FFFFF64 KB
I2C0_CFG0x00020000000x00020000FF256 B
I2C1_CFG0x00020100000x00020100FF256 B
I2C2_CFG0x00020200000x00020200FF256 B
I2C3_CFG0x00020300000x00020300FF256 B
I2C4_CFG0x00020400000x00020400FF256 B
I2C5_CFG0x00020500000x00020500FF256 B
I2C6_CFG0x00020600000x00020600FF256 B
I3C0_MMR_MMRVBP0x00020A00000x00020A01FF512 B
I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST0x00020A80000x00020A83FF1 KB
MCSPI0_CFG0x00021000000x00021003FF1 KB
MCSPI1_CFG0x00021100000x00021103FF1 KB
MCSPI2_CFG0x00021200000x00021203FF1 KB
MCSPI3_CFG0x00021300000x00021303FF1 KB
MCSPI4_CFG0x00021400000x00021403FF1 KB
MCSPI5_CFG0x00021500000x00021503FF1 KB
MCSPI6_CFG0x00021600000x00021603FF1 KB
MCSPI7_CFG0x00021700000x00021703FF1 KB
RTI0_CFG0x00022000000x00022000FF256 B
RTI1_CFG0x00022100000x00022100FF256 B
RTI15_CFG0x00022F00000x00022F00FF256 B
RTI16_CFG0x00023000000x00023000FF256 B
RTI24_CFG0x00023800000x00023800FF256 B
RTI25_CFG0x00023900000x00023900FF256 B
RTI28_CFG0x00023C00000x00023C00FF256 B
RTI29_CFG0x00023D00000x00023D00FF256 B
RTI30_CFG0x00023E00000x00023E00FF256 B
RTI31_CFG0x00023F00000x00023F00FF256 B
TIMER0_CFG0x00024000000x00024003FF1 KB
TIMER1_CFG0x00024100000x00024103FF1 KB
TIMER2_CFG0x00024200000x00024203FF1 KB
TIMER3_CFG0x00024300000x00024303FF1 KB
TIMER4_CFG0x00024400000x00024403FF1 KB
TIMER5_CFG0x00024500000x00024503FF1 KB
TIMER6_CFG0x00024600000x00024603FF1 KB
TIMER7_CFG0x00024700000x00024703FF1 KB
TIMER8_CFG0x00024800000x00024803FF1 KB
TIMER9_CFG0x00024900000x00024903FF1 KB
TIMER10_CFG0x00024A00000x00024A03FF1 KB
TIMER11_CFG0x00024B00000x00024B03FF1 KB
TIMER12_CFG0x00024C00000x00024C03FF1 KB
TIMER13_CFG0x00024D00000x00024D03FF1 KB
TIMER14_CFG0x00024E00000x00024E03FF1 KB
TIMER15_CFG0x00024F00000x00024F03FF1 KB
TIMER16_CFG0x00025000000x00025003FF1 KB
TIMER17_CFG0x00025100000x00025103FF1 KB
TIMER18_CFG0x00025200000x00025203FF1 KB
TIMER19_CFG0x00025300000x00025303FF1 KB
MCAN0_SS0x00027000000x00027000FF256 B
MCAN0_CFG0x00027010000x00027011FF512 B
MCAN0_MSGMEM_RAM0x00027080000x000270FFFF32 KB
MCAN1_SS0x00027100000x00027100FF256 B
MCAN1_CFG0x00027110000x00027111FF512 B
MCAN1_MSGMEM_RAM0x00027180000x000271FFFF32 KB
MCAN2_SS0x00027200000x00027200FF256 B
MCAN2_CFG0x00027210000x00027211FF512 B
MCAN2_MSGMEM_RAM0x00027280000x000272FFFF32 KB
MCAN3_SS0x00027300000x00027300FF256 B
MCAN3_CFG0x00027310000x00027311FF512 B
MCAN3_MSGMEM_RAM0x00027380000x000273FFFF32 KB
MCAN4_SS0x00027400000x00027400FF256 B
MCAN4_CFG0x00027410000x00027411FF512 B
MCAN4_MSGMEM_RAM0x00027480000x000274FFFF32 KB
MCAN5_SS0x00027500000x00027500FF256 B
MCAN5_CFG0x00027510000x00027511FF512 B
MCAN5_MSGMEM_RAM0x00027580000x000275FFFF32 KB
MCAN6_SS0x00027600000x00027600FF256 B
MCAN6_CFG0x00027610000x00027611FF512 B
MCAN6_MSGMEM_RAM0x00027680000x000276FFFF32 KB
MCAN7_SS0x00027700000x00027700FF256 B
MCAN7_CFG0x00027710000x00027711FF512 B
MCAN7_MSGMEM_RAM0x00027780000x000277FFFF32 KB
MCAN8_SS0x00027800000x00027800FF256 B
MCAN8_CFG0x00027810000x00027811FF512 B
MCAN8_MSGMEM_RAM0x00027880000x000278FFFF32 KB
MCAN9_SS0x00027900000x00027900FF256 B
MCAN9_CFG0x00027910000x00027911FF512 B
MCAN9_MSGMEM_RAM0x00027980000x000279FFFF32 KB
MCAN10_SS0x00027A00000x00027A00FF256 B
MCAN10_CFG0x00027A10000x00027A11FF512 B
MCAN10_MSGMEM_RAM0x00027A80000x00027AFFFF32 KB
MCAN11_SS0x00027B00000x00027B00FF256 B
MCAN11_CFG0x00027B10000x00027B11FF512 B
MCAN11_MSGMEM_RAM0x00027B80000x00027BFFFF32 KB
MCAN12_SS0x00027C00000x00027C00FF256 B
MCAN12_CFG0x00027C10000x00027C11FF512 B
MCAN12_MSGMEM_RAM0x00027C80000x00027CFFFF32 KB
MCAN13_SS0x00027D00000x00027D00FF256 B
MCAN13_CFG0x00027D10000x00027D11FF512 B
MCAN13_MSGMEM_RAM0x00027D80000x00027DFFFF32 KB
PDMA5_REGS0x00027E00000x00027E03FF1 KB
UART00x00028000000x00028001FF512 B
UART10x00028100000x00028101FF512 B
UART20x00028200000x00028201FF512 B
UART30x00028300000x00028301FF512 B
UART40x00028400000x00028401FF512 B
UART50x00028500000x00028501FF512 B
UART60x00028600000x00028601FF512 B
UART70x00028700000x00028701FF512 B
UART80x00028800000x00028801FF512 B
UART90x00028900000x00028901FF512 B
PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG0x00029000000x0002900FFF4 KB
PCIE0_CORE_VMAP_HP_MMRS0x00029040000x00029043FF1 KB
PCIE0_CORE_VMAP_LP_MMRS0x00029050000x00029053FF1 KB
PCIE0_CORE_CPTS_CFG_CPTS_VBUSP0x00029060000x00029063FF1 KB
PCIE0_CORE_USER_CFG_USER_CFG0x00029070000x00029073FF1 KB
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG0x00029100000x0002910FFF4 KB
PCIE1_CORE_VMAP_HP_MMRS0x00029140000x00029143FF1 KB
PCIE1_CORE_VMAP_LP_MMRS0x00029150000x00029153FF1 KB
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP0x00029160000x00029163FF1 KB
PCIE1_CORE_USER_CFG_USER_CFG0x00029170000x00029173FF1 KB
PCIE2_CORE_PCIE_INTD_CFG_INTD_CFG0x00029200000x0002920FFF4 KB
PCIE2_CORE_VMAP_HP_MMRS0x00029240000x00029243FF1 KB
PCIE2_CORE_VMAP_LP_MMRS0x00029250000x00029253FF1 KB
PCIE2_CORE_CPTS_CFG_CPTS_VBUSP0x00029260000x00029263FF1 KB
PCIE2_CORE_USER_CFG_USER_CFG0x00029270000x00029273FF1 KB
PCIE3_CORE_PCIE_INTD_CFG_INTD_CFG0x00029300000x0002930FFF4 KB
PCIE3_CORE_VMAP_HP_MMRS0x00029340000x00029343FF1 KB
PCIE3_CORE_VMAP_LP_MMRS0x00029350000x00029353FF1 KB
PCIE3_CORE_CPTS_CFG_CPTS_VBUSP0x00029360000x00029363FF1 KB
PCIE3_CORE_USER_CFG_USER_CFG0x00029370000x00029373FF1 KB
COMPUTE_CLUSTER0_SS_CFG0x00029800000x00029801FF512 B
COMPUTE_CLUSTER0_CTL_CFG0x00029900000x0002997FFF32 KB
PCIE0_CORE_ECC_AGGR00x0002A000000x0002A003FF1 KB
PCIE0_CORE_ECC_AGGR10x0002A010000x0002A013FF1 KB
PCIE1_CORE_ECC_AGGR00x0002A020000x0002A023FF1 KB
PCIE1_CORE_ECC_AGGR10x0002A030000x0002A033FF1 KB
PCIE2_CORE_ECC_AGGR00x0002A040000x0002A043FF1 KB
PCIE2_CORE_ECC_AGGR10x0002A050000x0002A053FF1 KB
PCIE3_CORE_ECC_AGGR00x0002A060000x0002A063FF1 KB
PCIE3_CORE_ECC_AGGR10x0002A070000x0002A073FF1 KB
USB0_RAMS_INJ_CFG0x0002A100000x0002A103FF1 KB
USB0_ECC_AGGR0x0002A130000x0002A133FF1 KB
USB1_ECC_AGGR0x0002A160000x0002A163FF1 KB
USB1_RAMS_INJ_CFG0x0002A170000x0002A173FF1 KB
CPSW0_ECC0x0002A210000x0002A213FF1 KB
SA2_UL0_ECC_AGGR0x0002A230000x0002A233FF1 KB
MMCSD0_ECC_AGGR_RXMEM0x0002A240000x0002A243FF1 KB
MMCSD0_ECC_AGGR_TXMEM0x0002A250000x0002A253FF1 KB
MMCSD1_ECC_AGGR_RXMEM0x0002A260000x0002A263FF1 KB
MMCSD1_ECC_AGGR_TXMEM0x0002A270000x0002A273FF1 KB
UFS0_HCLK_ECC_AGGR_CFG0x0002A280000x0002A283FF1 KB
UFS0_IPS_TCLK_ERR_INJ_CFG0x0002A2A0000x0002A2A3FF1 KB
MSRAM16KX256E0_ECC_AGGR_REGS0x0002A2F0000x0002A2F3FF1 KB
CSI_RX_IF0_ECC_AGGR_CFG0x0002A300000x0002A303FF1 KB
CSI_RX_IF1_ECC_AGGR_CFG0x0002A310000x0002A313FF1 KB
CSI_TX_IF0_ECC_AGGR_CFG0x0002A380000x0002A383FF1 KB
CSI_TX_IF0_ECC_AGGR_BYTE_CFG0x0002A384000x0002A387FF1 KB
MCAN8_ECC_AGGR0x0002A400000x0002A403FF1 KB
MCAN9_ECC_AGGR0x0002A410000x0002A413FF1 KB
MCAN10_ECC_AGGR0x0002A420000x0002A423FF1 KB
MCAN11_ECC_AGGR0x0002A430000x0002A433FF1 KB
MCAN12_ECC_AGGR0x0002A440000x0002A443FF1 KB
MCAN13_ECC_AGGR0x0002A450000x0002A453FF1 KB
VPAC0_KSDW_ECC_AGGR_CFG0x0002A600000x0002A603FF1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG0x0002A610000x0002A613FF1 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_KSDW_ECC_AGGR_CFG0x0002A630000x0002A633FF1 KB
R5FSS0_CORE0_ECC_AGGR0x0002A680000x0002A683FF1 KB
R5FSS1_CORE0_ECC_AGGR0x0002A690000x0002A693FF1 KB
DMPAC0_KSDW_ECC_AGGR_CFG0x0002A6A0000x0002A6A3FF1 KB
MMCSD2_ECC_AGGR_TXMEM0x0002A700000x0002A703FF1 KB
MMCSD2_ECC_AGGR_RXMEM0x0002A710000x0002A713FF1 KB
I3C0_P_ECC_AGGR_CFG0x0002A740000x0002A743FF1 KB
I3C0_S_ECC_AGGR_CFG0x0002A750000x0002A753FF1 KB
MCAN0_ECC_AGGR0x0002A780000x0002A783FF1 KB
MCAN1_ECC_AGGR0x0002A790000x0002A793FF1 KB
MCAN2_ECC_AGGR0x0002A7A0000x0002A7A3FF1 KB
MCAN3_ECC_AGGR0x0002A7B0000x0002A7B3FF1 KB
MCAN4_ECC_AGGR0x0002A7C0000x0002A7C3FF1 KB
MCAN5_ECC_AGGR0x0002A7D0000x0002A7D3FF1 KB
MCAN6_ECC_AGGR0x0002A7E0000x0002A7E3FF1 KB
MCAN7_ECC_AGGR0x0002A7F0000x0002A7F3FF1 KB
CBASS_DEBUG0_ERR0x0002A800000x0002A803FF1 KB
CBASS_HC2_0_ERR0x0002A830000x0002A833FF1 KB
CBASS_AC_CFG0_ERR0x0002A840000x0002A843FF1 KB
CBASS_AC0_ERR0x0002A850000x0002A853FF1 KB
CBASS_DATADEBUG0_ERR0x0002A860000x0002A863FF1 KB
CBASS_HC0_ERR0x0002A870000x0002A873FF1 KB
CBASS_CSI0_ERR0x0002A880000x0002A883FF1 KB
CBASS_HC_CFG0_ERR0x0002A890000x0002A893FF1 KB
CBASS_MCASP_G0_0_ERR0x0002A8A0000x0002A8A3FF1 KB
CBASS_MCASP_G1_0_ERR0x0002A8B0000x0002A8B3FF1 KB
CBASS_RC0_ERR0x0002A8C0000x0002A8C3FF1 KB
CBASS_RC_CFG0_ERR0x0002A8D0000x0002A8D3FF1 KB
CBASS_AASRC0_ERR0x0002A8E0000x0002A8E3FF1 KB
CBASS_IPPHY0_ERR0x0002A8F0000x0002A8F3FF1 KB
DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG0x0002AC00000x0002AC03FF1 KB
DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG0x0002AC10000x0002AC13FF1 KB
DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG0x0002AC20000x0002AC23FF1 KB
ECC_AGGR16_REGS0x0002AF00000x0002AF03FF1 KB
ECC_AGGR17_REGS0x0002AF10000x0002AF13FF1 KB
ECC_AGGR18_REGS0x0002AF20000x0002AF23FF1 KB
ECC_AGGR19_REGS0x0002AF30000x0002AF33FF1 KB
ECC_AGGR4_REGS0x0002AF40000x0002AF43FF1 KB
ECC_AGGR5_REGS0x0002AF50000x0002AF53FF1 KB
ECC_AGGR6_REGS0x0002AF60000x0002AF63FF1 KB
ECC_AGGR10_REGS0x0002AFA0000x0002AFA3FF1 KB
ECC_AGGR11_REGS0x0002AFB0000x0002AFB3FF1 KB
MCASP0_CFG0x0002B000000x0002B01FFF8 KB
MCASP0_DMA0x0002B080000x0002B083FF1 KB
MCASP1_CFG0x0002B100000x0002B11FFF8 KB
MCASP1_DMA0x0002B180000x0002B183FF1 KB
MCASP2_CFG0x0002B200000x0002B21FFF8 KB
MCASP2_DMA0x0002B280000x0002B283FF1 KB
MCASP3_CFG0x0002B300000x0002B31FFF8 KB
MCASP3_DMA0x0002B380000x0002B383FF1 KB
MCASP4_CFG0x0002B400000x0002B41FFF8 KB
MCASP4_DMA0x0002B480000x0002B483FF1 KB
MCASP5_CFG0x0002B500000x0002B51FFF8 KB
MCASP5_DMA0x0002B580000x0002B583FF1 KB
MCASP6_CFG0x0002B600000x0002B61FFF8 KB
MCASP6_DMA0x0002B680000x0002B683FF1 KB
MCASP7_CFG0x0002B700000x0002B71FFF8 KB
MCASP7_DMA0x0002B780000x0002B783FF1 KB
MCASP8_CFG0x0002B800000x0002B81FFF8 KB
MCASP8_DMA0x0002B880000x0002B883FF1 KB
MCASP9_CFG0x0002B900000x0002B91FFF8 KB
MCASP9_DMA0x0002B980000x0002B983FF1 KB
MCASP10_CFG0x0002BA00000x0002BA1FFF8 KB
MCASP10_DMA0x0002BA80000x0002BA83FF1 KB
MCASP11_CFG0x0002BB00000x0002BB1FFF8 KB
MCASP11_DMA0x0002BB80000x0002BB83FF1 KB
AASRC0_CFG0x0002D000000x0002D03FFF16 KB
AASRC0_DATA_R00x0002D100000x0002D13FFF16 KB
AASRC0_DATA_R10x0002D200000x0002D23FFF16 KB
VPFE0_MMRS0x0002F000000x0002F00FFF4 KB
VPFE0_VPFE0x0002F080000x0002F08FFF4 KB
MLB0_MMR_MMRVBP0x0002F800000x0002F801FF512 B
MLB0_MLBDIM_WRAP_ECC_AGGR_VBP0x0002F810000x0002F813FF1 KB
MLB0_VBP2APB_WRAP_MLB_CFG_VBP_MLBDIM0x0002F820000x0002F823FF1 KB
MLB0_RAT_WRAP_RAT_CFG_VBP_MMRS0x0002F830000x0002F83FFF4 KB
EHRPWM0_EPWM0x00030000000x00030000FF256 B
EHRPWM0_EHRPWM0x00030080000x00030080FF256 B
EHRPWM1_EPWM0x00030100000x00030100FF256 B
EHRPWM1_EHRPWM0x00030180000x00030180FF256 B
EHRPWM2_EPWM0x00030200000x00030200FF256 B
EHRPWM2_EHRPWM0x00030280000x00030280FF256 B
EHRPWM3_EPWM0x00030300000x00030300FF256 B
EHRPWM3_EHRPWM0x00030380000x00030380FF256 B
EHRPWM4_EPWM0x00030400000x00030400FF256 B
EHRPWM4_EHRPWM0x00030480000x00030480FF256 B
EHRPWM5_EPWM0x00030500000x00030500FF256 B
EHRPWM5_EHRPWM0x00030580000x00030580FF256 B
ECAP0_CTL_STS0x00031000000x00031000FF256 B
ECAP1_CTL_STS0x00031100000x00031100FF256 B
ECAP2_CTL_STS0x00031200000x00031200FF256 B
ATL0_REG0x00031F00000x00031F03FF1 KB
EQEP0_REG0x00032000000x00032000FF256 B
EQEP1_REG0x00032100000x00032100FF256 B
EQEP2_REG0x00032200000x00032200FF256 B
PBIST10x00033000000x00033003FF1 KB
PBIST30x00033100000x00033103FF1 KB
PBIST00x00033200000x00033203FF1 KB
PBIST20x00033300000x00033303FF1 KB
PBIST40x00033400000x00033403FF1 KB
PBIST70x00033600000x00033603FF1 KB
PBIST50x00033700000x00033703FF1 KB
PBIST90x00033800000x00033803FF1 KB
PBIST100x00033900000x00033903FF1 KB
GPU0_PBIST_CFG0x00033A00000x00033A03FF1 KB
USART_PSILSS16_MMRS0x00034000000x0003400FFF4 KB
MISC_PSILSS12_MMRS0x00034040000x0003404FFF4 KB
DEBUG_PSILSS4_MMRS0x00034080000x0003408FFF4 KB
AASRC_PSILSS1_MMRS0x000340C0000x000340CFFF4 KB
CSI_PSILSS0_MMRS0x00034100000x0003410FFF4 KB
MSRAM16KX256E0_RAM0x00036000000x000367FFFF512 KB
NAVSS0_NBSS_CFG_REGS0_MMRS0x00038000000x00038000FF256 B
NAVSS0_NBSS_CFG_ECCAGGR0_REGS0x00038010000x00038013FF1 KB
NAVSS0_NBSS_NB0_CFG_MMRS0x00038020000x00038020FF256 B
NAVSS0_NBSS_NB1_CFG_MMRS0x00038030000x00038030FF256 B
NAVSS0_NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS0x00038100000x00038100FF256 B
USB0_MMR_MMRVBP_USBSS_CMN0x00041040000x00041040FF256 B
USB0_PHY20x00041080000x00041083FF1 KB
USB1_MMR_MMRVBP_USBSS_CMN0x00041140000x00041140FF256 B
USB1_PHY20x00041180000x00041183FF1 KB
ENCODER0_REG_AXI0x00042050000x00042053FF1 KB
DECODER0_IMG_VIDEO_BUS4_MMU0x00043010000x00043011FF512 B
DECODER0_MSVDX_AXI0x00043018000x00043018078 B
DECODER0_IMG_VIDEO_BUS4_MMU20x00043210000x00043211FF512 B
DECODER0_MSVDX_AXI20x00043218000x00043218078 B
CSI_TX_IF0_TX_SHIM_VBUSP_MMR_CSI2TXIF0x00044000000x0004400FFF4 KB
CSI_TX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX0x00044040000x0004404FFF4 KB
CSI_TX_IF0_CP_INTD_CFG_INTD_CFG0x00044080000x0004408FFF4 KB
DPHY_TX00x00044800000x0004480FFF4 KB
CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF0x00045000000x0004500FFF4 KB
CSI_RX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX0x00045040000x0004504FFF4 KB
CSI_RX_IF0_CP_INTD_CFG_INTD_CFG0x00045080000x0004508FFF4 KB
CSI_RX_IF1_RX_SHIM_VBUSP_MMR_CSI2RXIF0x00045100000x0004510FFF4 KB
CSI_RX_IF1_VBUS2APB_WRAP_VBUSP_APB_CSI2RX0x00045140000x0004514FFF4 KB
CSI_RX_IF1_CP_INTD_CFG_INTD_CFG0x00045180000x0004518FFF4 KB
DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX0x00045800000x0004580FFF4 KB
DPHY_RX0_MMR_SLV_K3_DPHY_WRAP0x00045810000x00045810FF256 B
DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX0x00045900000x0004590FFF4 KB
DPHY_RX1_MMR_SLV_K3_DPHY_WRAP0x00045910000x00045910FF256 B
DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG0x00047000000x00047003FF1 KB
DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP0x00047100000x00047100FF256 B
DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI0x00048000000x00048FFFFF1 MB
DSS0_DISPC_0_COMMON_M0x0004A000000x0004A0FFFF64 KB
DSS0_VIDL10x0004A200000x0004A2FFFF64 KB
DSS0_VIDL20x0004A300000x0004A3FFFF64 KB
DSS0_VID10x0004A500000x0004A5FFFF64 KB
DSS0_VID20x0004A600000x0004A6FFFF64 KB
DSS0_OVR10x0004A700000x0004A7FFFF64 KB
DSS0_VP10x0004A800000x0004A8FFFF64 KB
DSS0_OVR20x0004A900000x0004A9FFFF64 KB
DSS0_VP20x0004AA00000x0004AAFFFF64 KB
DSS0_OVR30x0004AB00000x0004ABFFFF64 KB
DSS0_VP30x0004AC00000x0004ACFFFF64 KB
DSS0_OVR40x0004AD00000x0004ADFFFF64 KB
DSS0_VP40x0004AE00000x0004AEFFFF64 KB
DSS0_WB0x0004AF00000x0004AFFFFF64 KB
SA2_UL00x0004E000000x0004E00FFF4 KB
SA2_UL0_MMRA0x0004E010000x0004E011FF512 B
SA2_UL0_EIP_760x0004E100000x0004E1007F128 B
SA2_UL0_EIP_29T20x0004E200000x0004E2FFFF64 KB
UFS0_SYSCFG_SS_CFG0x0004E800000x0004E800FF256 B
UFS0_P2A_WRAP_CFG_VBP_UFSHCI0x0004E840000x0004E85FFF8 KB
DSS_EDP0_INTG_CFG_VP0x0004F400000x0004F400FF256 B
DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB0x0004F480000x0004F480FF256 B
MMCSD0_CTL_CFG0x0004F800000x0004F80FFF4 KB
MMCSD0_SS_CFG0x0004F880000x0004F883FF1 KB
MMCSD2_SS_CFG0x0004F900000x0004F903FF1 KB
MMCSD2_CTL_CFG0x0004F980000x0004F98FFF4 KB
MMCSD1_CTL_CFG0x0004FB00000x0004FB0FFF4 KB
MMCSD1_SS_CFG0x0004FB80000x0004FB83FF1 KB
SERDES_16G00x00050000000x000500FFFF64 KB
SERDES_16G10x00050100000x000501FFFF64 KB
SERDES_16G20x00050200000x000502FFFF64 KB
SERDES_16G30x00050300000x000503FFFF64 KB
SERDES_10G00x00050500000x000505FFFF64 KB
ELM00x00053800000x0005380FFF4 KB
GPMC0_CFG0x00053900000x00053903FF1 KB
R5FSS0_COMPARE_CFG0x0005B000000x0005B000FF256 B
R5FSS0_ECC_AGGR0x0005B100000x0005B103FF1 KB
R5FSS1_COMPARE_CFG0x0005B200000x0005B200FF256 B
R5FSS1_ECC_AGGR0x0005B300000x0005B303FF1 KB
R5FSS0_CORE0_ATCM0x0005C000000x0005C07FFF32 KB
R5FSS0_CORE0_BTCM0x0005C100000x0005C17FFF32 KB
R5FSS0_CORE1_ATCM(1)0x0005D000000x0005D07FFF32 KB
R5FSS0_CORE1_BTCM(1)0x0005D100000x0005D17FFF32 KB
R5FSS1_CORE0_ATCM0x0005E000000x0005E07FFF32 KB
R5FSS1_CORE0_BTCM0x0005E100000x0005E17FFF32 KB
R5FSS1_CORE1_ATCM(1)0x0005F000000x0005F07FFF32 KB
R5FSS1_CORE1_BTCM(1)0x0005F100000x0005F17FFF32 KB
USB0_VBP2APB_WRAP_CONTROLLER_VBP_CORE_ADDR_MAP0x00060000000x00063FFFFF4 MB
USB1_VBP2APB_WRAP_CONTROLLER_VBP_CORE_ADDR_MAP0x00064000000x00067FFFFF4 MB
DEBUGSS1_SYS0x00080000000x0008000FFF4 KB
DEBUGSS0_SYS0x00080040000x0008004FFF4 KB
CCDEBUGSS0_SYS0x00080080000x0008008FFF4 KB
C66DEBUGSS0_SYS0x00080100000x0008010FFF4 KB
C66DEBUGSS1_SYS0x00080200000x0008020FFF4 KB
STM0_STIMULUS0x00090000000x0009FFFFFF16 MB
DSS_EDP0_V2A_CORE_VP_REGS_APB0x000A0000000x000A03FFFF256 KB
PRU_ICSSG0_DRAM0_SLV_RAM0x000B0000000x000B001FFF8 KB
PRU_ICSSG0_DRAM1_SLV_RAM0x000B0020000x000B003FFF8 KB
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM0x000B0040000x000B005FFF8 KB
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM0x000B0060000x000B007FFF8 KB
PRU_ICSSG0_RAT_SLICE0_CFG0x000B0080000x000B008FFF4 KB
PRU_ICSSG0_RAT_SLICE1_CFG0x000B0090000x000B009FFF4 KB
PRU_ICSSG0_RAM_SLV_RAM0x000B0100000x000B01FFFF64 KB
PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV0x000B0200000x000B021FFF8 KB
PRU_ICSSG0_PR1_PDSP0_IRAM0x000B0220000x000B0220FF256 B
PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG0x000B0224000x000B0224FF256 B
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM0x000B0230000x000B0230FF256 B
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG0x000B0234000x000B0234FF256 B
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM0x000B0238000x000B0238FF256 B
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG0x000B023C000x000B023CFF256 B
PRU_ICSSG0_PR1_PDSP1_IRAM0x000B0240000x000B0240FF256 B
PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG0x000B0244000x000B0244FF256 B
PRU_ICSSG0_PR1_PROT_SLV0x000B024C000x000B024CFF256 B
PRU_ICSSG0_PR1_CFG_SLV0x000B0260000x000B0261FF512 B
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_QSTAT0x000B0270000x000B027FFF4 KB
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV0x000B0280000x000B02803F64 B
PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR0x000B02A0000x000B02A0FF256 B
PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR0x000B02A1000x000B02A1FF256 B
PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR0x000B02A2000x000B02A2FF256 B
PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR0x000B02A3000x000B02A3FF256 B
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV_CSTAT0x000B02C0000x000B02CFFF4 KB
PRU_ICSSG0_IEP00x000B02E0000x000B02EFFF4 KB
PRU_ICSSG0_IEP10x000B02F0000x000B02FFFF4 KB
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV0x000B0300000x000B0300FF256 B
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG0x000B0320000x000B0320FF256 B
PRU_ICSSG0_PR1_MII_RT_PR1_SGMII0_CFG_SGMII00x000B0321000x000B0321FF256 B
PRU_ICSSG0_PR1_MII_RT_PR1_SGMII1_CFG_SGMII10x000B0322000x000B0322FF256 B
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO0x000B0324000x000B0324FF256 B
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G0x000B0330000x000B033FFF4 KB
PRU_ICSSG0_PR1_PDSP0_IRAM_RAM0x000B0340000x000B037FFF16 KB
PRU_ICSSG0_PR1_PDSP1_IRAM_RAM0x000B0380000x000B03BFFF16 KB
PRU_ICSSG0_PA_STAT_WRAP_PA_SLV0x000B03C0000x000B03C0FF256 B
PRU_ICSSG1_DRAM0_SLV_RAM0x000B1000000x000B101FFF8 KB
PRU_ICSSG1_DRAM1_SLV_RAM0x000B1020000x000B103FFF8 KB
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM0x000B1040000x000B105FFF8 KB
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM0x000B1060000x000B107FFF8 KB
PRU_ICSSG1_RAT_SLICE0_CFG0x000B1080000x000B108FFF4 KB
PRU_ICSSG1_RAT_SLICE1_CFG0x000B1090000x000B109FFF4 KB
PRU_ICSSG1_RAM_SLV_RAM0x000B1100000x000B11FFFF64 KB
PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV0x000B1200000x000B121FFF8 KB
PRU_ICSSG1_PR1_PDSP0_IRAM0x000B1220000x000B1220FF256 B
PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG0x000B1224000x000B1224FF256 B
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM0x000B1230000x000B1230FF256 B
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG0x000B1234000x000B1234FF256 B
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM0x000B1238000x000B1238FF256 B
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG0x000B123C000x000B123CFF256 B
PRU_ICSSG1_PR1_PDSP1_IRAM0x000B1240000x000B1240FF256 B
PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG0x000B1244000x000B1244FF256 B
PRU_ICSSG1_PR1_PROT_SLV0x000B124C000x000B124CFF256 B
PRU_ICSSG1_PR1_CFG_SLV0x000B1260000x000B1261FF512 B
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_QSTAT0x000B1270000x000B127FFF4 KB
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV0x000B1280000x000B12803F64 B
PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR0x000B12A0000x000B12A0FF256 B
PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR0x000B12A1000x000B12A1FF256 B
PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR0x000B12A2000x000B12A2FF256 B
PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR0x000B12A3000x000B12A3FF256 B
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV_CSTAT0x000B12C0000x000B12CFFF4 KB
PRU_ICSSG1_IEP00x000B12E0000x000B12EFFF4 KB
PRU_ICSSG1_IEP10x000B12F0000x000B12FFFF4 KB
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV0x000B1300000x000B1300FF256 B
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG0x000B1320000x000B1320FF256 B
PRU_ICSSG1_PR1_MII_RT_PR1_SGMII0_CFG_SGMII00x000B1321000x000B1321FF256 B
PRU_ICSSG1_PR1_MII_RT_PR1_SGMII1_CFG_SGMII10x000B1322000x000B1322FF256 B
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO0x000B1324000x000B1324FF256 B
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G0x000B1330000x000B133FFF4 KB
PRU_ICSSG1_PR1_PDSP0_IRAM_RAM0x000B1340000x000B137FFF16 KB
PRU_ICSSG1_PR1_PDSP1_IRAM_RAM0x000B1380000x000B13BFFF16 KB
PRU_ICSSG1_PA_STAT_WRAP_PA_SLV0x000B13C0000x000B13C0FF256 B
PRU_ICSSG0_ECC_AGGR0x000BF000000x000BF003FF1 KB
PRU_ICSSG1_ECC_AGGR0x000BF010000x000BF013FF1 KB
CPSW0_NUSS0x000C0000000x000C1FFFFF2 MB
PCIE0_CORE_DBN_CFG_PCIE_CORE0x000D0000000x000D7FFFFF8 MB
PCIE1_CORE_DBN_CFG_PCIE_CORE0x000D8000000x000DFFFFFF8 MB
PCIE2_CORE_DBN_CFG_PCIE_CORE0x000E0000000x000E7FFFFF8 MB
PCIE3_CORE_DBN_CFG_PCIE_CORE0x000E8000000x000EFFFFFF8 MB
VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS0x000F0000000x000F0003FF1 KB
VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG0x000F0020000x000F003FFF8 KB
VPAC0_CP_INTD_CFG_INTD_CFG0x000F0040000x000F004FFF4 KB
VPAC0_HTS_S_VBUSP0x000F0080000x000F00FFFF32 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP0x000F0200000x000F0203FF1 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP0x000F0204000x000F0205FF512 B
VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT0x000F0208000x000F020FFF2 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT0x000F0210000x000F0217FF2 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM0x000F0220000x000F023FFF8 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM0x000F0280000x000F02FFFF32 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM0x000F0300000x000F037FFF32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP0x000F0800000x000F0801FF512 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP0x000F0804000x000F0805FF512 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE0x000F0838000x000F083FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM0x000F0840000x000F087FFF16 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA0x000F0880000x000F08FFFF32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC0x000F0900000x000F0907FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC10x000F0908000x000F090FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC20x000F0910000x000F0917FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC30x000F0918000x000F091FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R80x000F0920000x000F0927FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G80x000F0928000x000F092FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B80x000F0930000x000F0937FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST0x000F0938000x000F093FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE0x000F0980000x000F0987FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG0x000F0A00000x000F0A03FF1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG0x000F0A04000x000F0A04FF256 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT3_RAM_RAWFE_PWL_LUT3_RAM0x000F0A08000x000F0A0FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT2_RAM_RAWFE_PWL_LUT2_RAM0x000F0A10000x000F0A17FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT1_RAM_RAWFE_PWL_LUT1_RAM0x000F0A18000x000F0A1FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_WDR_LUT_RAM_RAWFE_WDR_LUT_RAM0x000F0A20000x000F0A27FF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_LUT_RAM_RAWFE_H3A_LUT_RAM0x000F0A28000x000F0A2FFF2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_RAM_RAWFE_DPC_LUT_RAM0x000F0A30000x000F0A33FF1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_LRAM_RAWFE_DPC_LRAM0x000F0A40000x000F0A5FFF8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LSC_RAM_RAWFE_LSC_LUT_RAM0x000F0A80000x000F0AFFFF32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_ARAM_RAWFE_H3A_ARAM0x000F0B00000x000F0B1FFF8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_LRAM_RAWFE_H3A_LRAM0x000F0B20000x000F0B3FFF8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE0x000F0C00000x000F0C03FF1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM0x000F0C40000x000F0C7FFF16 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE0x000F0D00000x000F0D7FFF32 KB
VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP0x000F1C00000x000F1C07FF2 KB
VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP0x000F1C08000x000F1C09FF512 B
VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG0x000F1C20000x000F1C2FFF4 KB
VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP0x000F1C30000x000F1C31FF512 B
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU0x000F2000000x000F203FFF16 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET0x000F2040000x000F207FFF16 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE0x000F2080000x000F20FFFF32 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT0x000F2400000x000F25FFFF128 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT0x000F2600000x000F27FFFF128 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG0x000F2800000x000F29FFFF128 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE0x000F2E00000x000F2FFFFF128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU0x000F3000000x000F303FFF16 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET0x000F3040000x000F307FFF16 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE0x000F3080000x000F30FFFF32 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT0x000F3400000x000F35FFFF128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT0x000F3600000x000F37FFFF128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG0x000F3800000x000F39FFFF128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE0x000F3E00000x000F3FFFFF128 KB
DMPAC0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS0x000F4000000x000F4003FF1 KB
DMPAC0_CP_INTD_CFG_INTD_CFG0x000F4010000x000F401FFF4 KB
DMPAC0_HTS_S_VBUSP0x000F4080000x000F40FFFF32 KB
DMPAC0_CTSET2_WRAP_CFG_CTSET2_CFG0x000F4200000x000F421FFF8 KB
DMPAC0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS0x000F4240000x000F42403F64 B
DMPAC0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP0x000F4242000x000F4243FF512 B
DMPAC0_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS0x000F4280000x000F42803F64 B
DMPAC0_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP0x000F4282000x000F4283FF512 B
DMPAC0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE0x000F4800000x000F480FFF4 KB
DMPAC0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM0x000F4C00000x000F4FFFFF256 KB
DMPAC0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR0x000F5000000x000F500FFF4 KB
DMPAC0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM0x000F5400000x000F57FFFF256 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU0x000F6000000x000F603FFF16 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET0x000F6040000x000F607FFF16 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE0x000F6080000x000F60FFFF32 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT0x000F6400000x000F65FFFF128 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT0x000F6600000x000F67FFFF128 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG0x000F6800000x000F69FFFF128 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE0x000F6E00000x000F6FFFFF128 KB
PCIE0_DAT00x00100000000x0017FFFFFF128 MB
PCIE1_DAT00x00180000000x001FFFFFFF128 MB
GPMC0_DATA0x00200000000x0027FFFFFF128 MB
NAVSS0_MSRAM0_SLV_RAM0x00300000000x003000FFFF64 KB
NAVSS0_MODSS_INTA0_CFG0x00308000000x003080001F32 B
NAVSS0_MODSS_INTA1_CFG0x00308010000x003080101F32 B
NAVSS0_UDMASS_INTA0_CFG0x00308020000x003080201F32 B
NAVSS0_MODSS_INTA0_CFG_IMAP0x00309000000x0030907FFF32 KB
NAVSS0_MODSS_INTA1_CFG_IMAP0x00309080000x003090FFFF32 KB
NAVSS0_UDMASS_INTA0_IMAP0x00309400000x003097FFFF256 KB
NAVSS0_NAV_DDR0_VIRTID_CFG_MMRS0x0030A020000x0030A020FF256 B
NAVSS0_NAV_DDR1_VIRTID_CFG_MMRS0x0030A030000x0030A030FF256 B
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN0x0030B000000x0030B1FFFF128 KB
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN0x0030C000000x0030C0FFFF64 KB
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW0x0030D000000x0030D07FFF32 KB
NAVSS0_SPINLOCK0x0030E000000x0030E07FFF32 KB
NAVSS0_TIMERMGR0_CFG0x0030E800000x0030E801FF512 B
NAVSS0_TIMERMGR1_CFG0x0030E810000x0030E811FF512 B
NAVSS0_TIMERMGR0_CFG_OES0x0030F000000x0030F00FFF4 KB
NAVSS0_TIMERMGR1_CFG_OES0x0030F010000x0030F01FFF4 KB
NAVSS0_ECCAGGR0_REGS0x00310000000x00310003FF1 KB
NAVSS0_UDMASS_ECCAGGR0_CFG_REGS0x00310010000x00310013FF1 KB
NAVSS0_VIRTSS_ECCAGGR_CFG0x00310020000x00310023FF1 KB
NAVSS0_PAT0_CFG_MMRS0x00310100000x00310100FF256 B
NAVSS0_PAT1_CFG_MMRS0x00310110000x00310110FF256 B
NAVSS0_PAT2_CFG_MMRS0x00310120000x00310120FF256 B
NAVSS0_PAT3_CFG_MMRS0x00310130000x00310130FF256 B
NAVSS0_PAT4_CFG_MMRS0x00310140000x00310140FF256 B
NAVSS0_UDMASS_INTA0_CFG_GCNTCFG0x00310400000x0031043FFF16 KB
NAVSS0_UDMASS_RINGACC0_CFG0x00310800000x00310BFFFF256 KB
NAVSS0_CFG0x00310C00000x00310C00FF256 B
NAVSS0_CPTS0x00310D00000x00310D03FF1 KB
NAVSS0_INTR0_INTR_ROUTER_CFG0x00310E00000x00310E3FFF16 KB
NAVSS0_UDMASS_INTA0_CFG_L2G0x00311000000x0031100FFF4 KB
NAVSS0_UDMASS_INTA0_CFG_MCAST0x00311100000x0031113FFF16 KB
NAVSS0_PROXY0_CFG_BUF_CFG0x00311200000x00311200FF256 B
NAVSS0_PROXY_BUF0x00311300000x0031133FFF16 KB
NAVSS0_SEC_PROXY0_CFG_MMRS0x00311400000x00311400FF256 B
NAVSS0_UDMASS_UDMAP0_CFG0x00311500000x00311500FF256 B
NAVSS0_UDMASS_RINGACC0_GCFG0x00311600000x00311603FF1 KB
NAVSS0_PSILSS_LOCAL_CFG_MMRS0x00311700000x0031170FFF4 KB
NAVSS0_PSILSS_GLOBAL_CFG_MMRS0x00311800000x0031180FFF4 KB
NAVSS0_PSILSS_TR_CFG_MMRS0x00311900000x0031190FFF4 KB
NAVSS0_MCRC0x0031F700000x0031F70FFF4 KB
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY0x0031F780000x0031F781FF512 B
NAVSS0_MAILBOX_REGS00x0031F800000x0031F801FF512 B
NAVSS0_MAILBOX_REGS10x0031F810000x0031F811FF512 B
NAVSS0_MAILBOX_REGS20x0031F820000x0031F821FF512 B
NAVSS0_MAILBOX_REGS30x0031F830000x0031F831FF512 B
NAVSS0_MAILBOX_REGS40x0031F840000x0031F841FF512 B
NAVSS0_MAILBOX_REGS50x0031F850000x0031F851FF512 B
NAVSS0_MAILBOX_REGS60x0031F860000x0031F861FF512 B
NAVSS0_MAILBOX_REGS70x0031F870000x0031F871FF512 B
NAVSS0_MAILBOX_REGS80x0031F880000x0031F881FF512 B
NAVSS0_MAILBOX_REGS90x0031F890000x0031F891FF512 B
NAVSS0_MAILBOX_REGS100x0031F8A0000x0031F8A1FF512 B
NAVSS0_MAILBOX_REGS110x0031F8B0000x0031F8B1FF512 B
NAVSS0_UDMASS_RINGACC0_CFG_MON0x00320000000x003201FFFF128 KB
NAVSS0_TIMERMGR0_CFG_TIMERS0x00322000000x003223FFFF256 KB
NAVSS0_TIMERMGR1_CFG_TIMERS0x00322400000x003227FFFF256 KB
NAVSS0_SEC_PROXY0_CFG_RT0x00324000000x00324FFFFF1 MB
NAVSS0_SEC_PROXY0_CFG_SCFG0x00328000000x00328FFFFF1 MB
NAVSS0_SEC_PROXY0_SRC_TARGET_DATA0x0032C000000x0032CFFFFF1 MB
NAVSS0_PROXY_TARGET0_DATA0x00330000000x003303FFFF256 KB
NAVSS0_PROXY0_BUF_CFG0x00334000000x003343FFFF256 KB
NAVSS0_UDMASS_INTA0_CFG_GCNTRTI0x00338000000x00339FFFFF2 MB
NAVSS0_MODSS_INTA0_CFG_INTR0x0033C000000x0033C3FFFF256 KB
NAVSS0_MODSS_INTA1_CFG_INTR0x0033C400000x0033C7FFFF256 KB
NAVSS0_UDMASS_INTA0_CFG_INTR0x0033D000000x0033DFFFFF1 MB
NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT0x00340000000x00340FFFFF1 MB
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT0x00350000000x00351FFFFF2 MB
NAVSS0_PAT0_CFG_SCRATCH0x00362000000x003620FFFF64 KB
NAVSS0_PAT1_CFG_SCRATCH0x00362100000x003621FFFF64 KB
NAVSS0_PAT2_CFG_SCRATCH0x00362200000x003622FFFF64 KB
NAVSS0_PAT3_CFG_SCRATCH0x00362300000x0036231FFF8 KB
NAVSS0_PAT4_CFG_SCRATCH0x00362400000x0036241FFF8 KB
NAVSS0_PAT0_CFG_TABLE0x00364000000x003643FFFF256 KB
NAVSS0_PAT1_CFG_TABLE0x00364400000x003647FFFF256 KB
NAVSS0_PAT2_CFG_TABLE0x00364800000x00364BFFFF256 KB
NAVSS0_PAT3_CFG_TABLE0x00364C00000x00364C7FFF32 KB
NAVSS0_PAT4_CFG_TABLE0x00365000000x0036507FFF32 KB
NAVSS0_TCU_CFG0x00366000000x00367FFFFF2 MB
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS0x00380000000x00383FFFFF4 MB
NAVSS0_UDMASS_RINGACC0_CFG_RT0x003C0000000x003C3FFFFF4 MB
CBASS_INFRA0_FW0x00450000000x004501FFFF128 KB
COMPUTE_CLUSTER0_A72SS0_COMMON_FW0x00450404000x00450407FF1 KB
COMPUTE_CLUSTER0_C71SS0_L2_FW0x00450420000x00450423FF1 KB
COMPUTE_CLUSTER0_C71SS0_MDMA_FW0x00450424000x00450427FF1 KB
COMPUTE_CLUSTER0_DRU_FW0x00450470000x00450473FF1 KB
COMPUTE_CLUSTER0_DRU_MMR_FW0x00450480000x004504FFFF32 KB
CBASS_IPPHY0_FW0x00452000000x004523FFFF256 KB
CBASS_RC0_FW0x00452400000x0045243FFF16 KB
CBASS_RC_CFG0_FW0x00452500000x004525FFFF64 KB
CBASS_CSI0_FW0x00452600000x0045267FFF32 KB
CBASS_DATADEBUG0_FW0x00452680000x004526FFFF32 KB
CBASS_MCASP_G1_0_FW0x00452700000x0045277FFF32 KB
CBASS_HC0_FW0x00452780000x0045279FFF8 KB
CBASS_HC_CFG0_FW0x00452800000x0045287FFF32 KB
CBASS_MCASP_G0_0_FW0x00452880000x004528BFFF16 KB
CBASS_AASRC0_FW0x004528C0000x004528FFFF16 KB
CBASS_AC_CFG0_FW0x00452A00000x00452AFFFF64 KB
NAVSS0_UDMASS_DMSC_FW0x00454000000x004547FFFF512 KB
NAVSS0_MODSS_DMSC_FW0x00454800000x004549FFFF128 KB
NAVSS0_VIRTSS_DMSC_FW0x00454A00000x00454A7FFF32 KB
DMPAC0_CFG_DMSC_FW0x00455D80000x00455DBFFF16 KB
DMPAC0_SL2_DMSC_FW0x00455E00000x00455E0FFF4 KB
VPAC0_DMSC_VPAC_SCRPFW0x00455E80000x00455EBFFF16 KB
VPAC0_DMSC_VPAC_SCRMFW0x00455F00000x00455F0FFF4 KB
COMPUTE_CLUSTER0_DMSC_PRIVID0x00458300000x0045833FFF16 KB
VPAC0_DMSC_VPAC_SCRMISC0x00458600000x0045861FFF8 KB
COMPUTE_CLUSTER0_DMSC_EMULATION0x00459000000x0045903FFF16 KB
MAIN_SEC_MMR0_DBG_CTRL0x00459440000x0045947FFF16 KB
COMPUTE_CLUSTER0_DMSC_BOOT0x0045A000000x0045A0FFFF64 KB
MAIN_SEC_MMR0_BOOT_CTRL0x0045A400000x0045A43FFF16 KB
CBASS_AC0_GLB0x0045B080000x0045B083FF1 KB
NAVSS0_MODSS_DMSC_GLB0x0045B0A0000x0045B0A3FF1 KB
NAVSS0_UDMASS_DMSC_GLB0x0045B0B0000x0045B0B3FF1 KB
NAVSS0_VIRTSS_DMSC_GLB0x0045B0B8000x0045B0BBFF1 KB
CBASS_INFRA0_GLB0x0045B0C0000x0045B0C3FF1 KB
DMPAC0_CFG_DMSC_GLB0x0045B0D0000x0045B0D3FF1 KB
DMPAC0_SL2_DMSC_GLB0x0045B0D4000x0045B0D7FF1 KB
VPAC0_DMSC_VPAC_SCRMGLB0x0045B0D8000x0045B0DBFF1 KB
VPAC0_DMSC_VPAC_SCRPGLB0x0045B0DC000x0045B0DFFF1 KB
COMPUTE_CLUSTER0_A72SS0_COMMON_FW_GLB0x0045B104000x0045B107FF1 KB
COMPUTE_CLUSTER0_C71SS0_L2_FW_GLB0x0045B120000x0045B123FF1 KB
COMPUTE_CLUSTER0_C71SS0_MDMA_FW_GLB0x0045B124000x0045B127FF1 KB
COMPUTE_CLUSTER0_DRU_FW_GLB0x0045B170000x0045B173FF1 KB
COMPUTE_CLUSTER0_DRU_MMR_FW_GLB0x0045B180000x0045B183FF1 KB
CBASS_AASRC0_GLB0x0045B200000x0045B203FF1 KB
CBASS_CSI0_GLB0x0045B204000x0045B207FF1 KB
CBASS_DATADEBUG0_GLB0x0045B208000x0045B20BFF1 KB
CBASS_HC0_GLB0x0045B20C000x0045B20FFF1 KB
CBASS_HC_CFG0_GLB0x0045B210000x0045B213FF1 KB
CBASS_IPPHY0_GLB0x0045B214000x0045B217FF1 KB
CBASS_MCASP_G0_0_GLB0x0045B218000x0045B21BFF1 KB
CBASS_MCASP_G1_0_GLB0x0045B21C000x0045B21FFF1 KB
CBASS_RC0_GLB0x0045B220000x0045B223FF1 KB
CBASS_RC_CFG0_GLB0x0045B224000x0045B227FF1 KB
CBASS_HC2_0_GLB0x0045B228000x0045B22BFF1 KB
CBASS_AC_CFG0_GLB0x0045B22C000x0045B22FFF1 KB
COMPUTE_CLUSTER0_A72SS00x00600000000x0060FFFFFF16 MB
NAVSS0_SRAM00x00600000000x007FFFFFFF512 MB
NAVSS0_SRAM10x00600000000x007FFFFFFF512 MB
COMPUTE_CLUSTER0_RESERVED10x00610000000x0061FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED20x00620000000x0062FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED30x00630000000x0063FFFFFF16 MB
COMPUTE_CLUSTER0_C71SS00x00640000000x0064FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED50x00650000000x0065FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED60x00660000000x0066FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED70x00670000000x0067FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED80x00680000000x0068FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED90x00690000000x0069FFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED100x006A0000000x006AFFFFFF16 MB
COMPUTE_CLUSTER0_RESERVED110x006B0000000x006BFFFFFF16 MB
COMPUTE_CLUSTER0_CPU120x006C0000000x006CFFFFFF16 MB
COMPUTE_CLUSTER0_DRU_CFG0x006D0000000x006D003FFF16 KB
COMPUTE_CLUSTER0_DRU_SET0x006D0040000x006D007FFF16 KB
COMPUTE_CLUSTER0_DRU_QUEUE0x006D0080000x006D00FFFF32 KB
COMPUTE_CLUSTER0_DRU_MEM_ATT00x006D0100000x006D01FFFF64 KB
COMPUTE_CLUSTER0_DRU_MEM_ATT10x006D0200000x006D02FFFF64 KB
COMPUTE_CLUSTER0_DRU_MEM_ATT20x006D0300000x006D03FFFF64 KB
COMPUTE_CLUSTER0_DRU_CHNRT0x006D0400000x006D05FFFF128 KB
COMPUTE_CLUSTER0_DRU_CHRT0x006D0600000x006D07FFFF128 KB
COMPUTE_CLUSTER0_DRU_CHATOMIC_DEBUG0x006D0800000x006D09FFFF128 KB
COMPUTE_CLUSTER0_DRU_CHCORE0x006D0A00000x006D0BFFFF128 KB
COMPUTE_CLUSTER0_DRU_CAUSE0x006D0E00000x006D0FFFFF128 KB
COMPUTE_CLUSTER0_MSMC_CFGS00x006E0000000x006EFFFFFF16 MB
COMPUTE_CLUSTER0_UNALLOCATED00x006F0000000x006FFFFFFF16 MB
COMPUTE_CLUSTER0_MSMC_SRAM0x00700000000x00707FFFFF8 MB
COMPUTE_CLUSTER0_MSMC_ATOMIC_COUNTERS0x00740000000x0077FFFFFF64 MB
COMPUTE_CLUSTER0_CLEC_REGS0x00780000000x007FFFFFFF128 MB
NAVSS0_DDR0_MEM0x00800000000x00FFFFFFFF2 GB
NAVSS0_DDR1_MEM0x00800000000x00FFFFFFFF2 GB
NAVSS0_DDR0_MEM10x08000000000x0FFFFFFFFF32 GB
NAVSS0_DDR1_MEM10x08000000000x0FFFFFFFFF32 GB
PCIE0_DAT10x40000000000x40FFFFFFFF4 GB
PCIE1_DAT10x41000000000x41FFFFFFFF4 GB
PCIE2_DAT10x42000000000x42FFFFFFFF4 GB
PCIE3_DAT10x43000000000x43FFFFFFFF4 GB
PCIE2_DAT00x44000000000x4407FFFFFF128 MB
PCIE3_DAT00x44100000000x4417FFFFFF128 MB
NAVSS0_PAT0_SRC_PAT0x48000000000x483FFFFFFF1 GB
NAVSS0_PAT1_SRC_PAT0x48400000000x487FFFFFFF1 GB
NAVSS0_PAT2_SRC_PAT0x48800000000x48BFFFFFFF1 GB
NAVSS0_PAT3_SRC_PAT0x49000000000x497FFFFFFF2 GB
NAVSS0_PAT4_SRC_PAT0x49800000000x49FFFFFFFF2 GB
NAVSS0 Alias Memory Map (See Table 2-2)0x4A1F7000000x4BFC3FFFFF7629 MB
DEBUGSS_WRAP0_ROM_TABLE_0_00x4C000000000x4C00000FFF4 KB
DEBUGSS_WRAP0_RESV0_00x4C000010000x4C00001FFF4 KB
DEBUGSS_WRAP0_CFGAP00x4C000020000x4C000020FF256 B
DEBUGSS_WRAP0_APBAP00x4C000021000x4C000021FF256 B
DEBUGSS_WRAP0_AXIAP00x4C000022000x4C000022FF256 B
DEBUGSS_WRAP0_PWRAP00x4C000023000x4C000023FF256 B
DEBUGSS_WRAP0_PVIEW00x4C000024000x4C000024FF256 B
DEBUGSS_WRAP0_JTAGAP00x4C000025000x4C000025FF256 B
DEBUGSS_WRAP0_SECAP00x4C000026000x4C000026FF256 B
DEBUGSS_WRAP0_CORTEX0_CFG00x4C000027000x4C000027FF256 B
DEBUGSS_WRAP0_CORTEX1_CFG00x4C000028000x4C000028FF256 B
DEBUGSS_WRAP0_CORTEX2_CFG00x4C000029000x4C000029FF256 B
DEBUGSS_WRAP0_CORTEX3_CFG00x4C00002A000x4C00002AFF256 B
DEBUGSS_WRAP0_CORTEX4_CFG00x4C00002B000x4C00002BFF256 B
DEBUGSS_WRAP0_CORTEX5_CFG00x4C00002C000x4C00002CFF256 B
DEBUGSS_WRAP0_CORTEX6_CFG00x4C00002D000x4C00002DFF256 B
DEBUGSS_WRAP0_CORTEX7_CFG00x4C00002E000x4C00002EFF256 B
DEBUGSS_WRAP0_CORTEX8_CFG00x4C00002F000x4C00002FFF256 B
DEBUGSS_WRAP0_RESV1_00x4C000030000x4C00003FFF4 KB
DEBUGSS_WRAP0_RESV2_00x4C000040000x4C02003FFF32 MB
DEBUGSS_WRAP0_ROM_TABLE_1_00x4C200000000x4C20000FFF4 KB
DEBUGSS_WRAP0_CSCTI00x4C200010000x4C20001FFF4 KB
DEBUGSS_WRAP0_DRM00x4C200020000x4C20002FFF4 KB
DEBUGSS_WRAP0_RESV3_00x4C200030000x4C20003FFF4 KB
DEBUGSS_WRAP0_CSTPIU00x4C200040000x4C20004FFF4 KB
DEBUGSS_WRAP0_CTF00x4C200050000x4C20005FFF4 KB
DEBUGSS_WRAP0_RESV4_00x4C200060000x4C21005FFF16 MB
COMPUTE_CLUSTER0_CCROM0x4C300000000x4C30000FFF4 KB
DEBUGSS_WRAP0_EXT_APB00x4C300000000x4C3FFFFFFF256 MB
COMPUTE_CLUSTER0_CTSET0x4C301000000x4C30101FFF8 KB
COMPUTE_CLUSTER0_CTI00x4C301020000x4C30102FFF4 KB
COMPUTE_CLUSTER0_CTI10x4C301030000x4C30103FFF4 KB
COMPUTE_CLUSTER0_CTI20x4C301040000x4C30104FFF4 KB
COMPUTE_CLUSTER0_CTI30x4C301050000x4C30105FFF4 KB
COMPUTE_CLUSTER0_CTI40x4C301060000x4C30106FFF4 KB
COMPUTE_CLUSTER0_CTI50x4C301070000x4C30107FFF4 KB
COMPUTE_CLUSTER0_CTI70x4C301090000x4C30109FFF4 KB
COMPUTE_CLUSTER0_AGGR00x4C301400000x4C3017FFFF256 KB
COMPUTE_CLUSTER0_AGGR10x4C301800000x4C301BFFFF256 KB
COMPUTE_CLUSTER0_CPAC00x4C304000000x4C307FFFFF4 MB
COMPUTE_CLUSTER0_CPAC40x4C314000000x4C317FFFFF4 MB
CCDEBUGSS0_ROM0x4C3C0000000x4C3C000FFF4 KB
CCDEBUGSS0_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG0x4C3C0040000x4C3C004FFF4 KB
CCDEBUGSS0_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG0x4C3C0050000x4C3C005FFF4 KB
CCDEBUGSS0_ARM_CTI_0_CFG_CSCTI_CFG0x4C3C0060000x4C3C006FFF4 KB
CCDEBUGSS0_ARM_CTI_1_CFG_CSCTI_CFG0x4C3C0080000x4C3C008FFF4 KB
CCDEBUGSS0_ARM_CTI_2_CFG_CSCTI_CFG0x4C3C0090000x4C3C009FFF4 KB
CCDEBUGSS0_ARM_CTI_3_CFG_CSCTI_CFG0x4C3C00A0000x4C3C00AFFF4 KB
CCDEBUGSS0_ARM_CTI_4_CFG_CSCTI_CFG0x4C3C00B0000x4C3C00BFFF4 KB
CCDEBUGSS0_ARM_CTI_5_CFG_CSCTI_CFG0x4C3C00C0000x4C3C00CFFF4 KB
CCDEBUGSS0_ARM_CTI_6_CFG_CSCTI_CFG0x4C3C00D0000x4C3C00DFFF4 KB
CCDEBUGSS0_ARM_CTI_7_CFG_CSCTI_CFG0x4C3C00E0000x4C3C00EFFF4 KB
CCDEBUGSS0_ARM_CTI_8_CFG_CSCTI_CFG0x4C3C00F0000x4C3C00FFFF4 KB
DEBUGSS0_ROM0x4C3C0100000x4C3C010FFF4 KB
DEBUGSS0_CTSET2_WRAP_CFG_CTSET2_CFG0x4C3C0120000x4C3C013FFF8 KB
DEBUGSS0_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG0x4C3C0140000x4C3C014FFF4 KB
DEBUGSS0_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG0x4C3C0150000x4C3C015FFF4 KB
DEBUGSS0_ARM_CTI_0_CFG_CSCTI_CFG0x4C3C0160000x4C3C016FFF4 KB
DEBUGSS0_ARM_CTI_1_CFG_CSCTI_CFG0x4C3C0180000x4C3C018FFF4 KB
DEBUGSS0_ARM_CTI_2_CFG_CSCTI_CFG0x4C3C0190000x4C3C019FFF4 KB
DEBUGSS0_ARM_CTI_3_CFG_CSCTI_CFG0x4C3C01A0000x4C3C01AFFF4 KB
DEBUGSS0_ARM_CTI_4_CFG_CSCTI_CFG0x4C3C01B0000x4C3C01BFFF4 KB
DEBUGSS0_ARM_CTI_5_CFG_CSCTI_CFG0x4C3C01C0000x4C3C01CFFF4 KB
DEBUGSS0_ARM_CTI_6_CFG_CSCTI_CFG0x4C3C01D0000x4C3C01DFFF4 KB
DEBUGSS0_ARM_CTI_7_CFG_CSCTI_CFG0x4C3C01E0000x4C3C01EFFF4 KB
DEBUGSS0_ARM_CTI_8_CFG_CSCTI_CFG0x4C3C01F0000x4C3C01FFFF4 KB
DEBUGSS1_ROM0x4C3C0200000x4C3C020FFF4 KB
DEBUGSS1_CTSET2_WRAP_CFG_CTSET2_CFG0x4C3C0220000x4C3C023FFF8 KB
DEBUGSS1_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG0x4C3C0240000x4C3C024FFF4 KB
DEBUGSS1_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG0x4C3C0250000x4C3C025FFF4 KB
DEBUGSS1_ARM_CTI_0_CFG_CSCTI_CFG0x4C3C0260000x4C3C026FFF4 KB
DEBUGSS1_ARM_CTI_1_CFG_CSCTI_CFG0x4C3C0280000x4C3C028FFF4 KB
DEBUGSS1_ARM_CTI_2_CFG_CSCTI_CFG0x4C3C0290000x4C3C029FFF4 KB
DEBUGSS1_ARM_CTI_3_CFG_CSCTI_CFG0x4C3C02A0000x4C3C02AFFF4 KB
DEBUGSS1_ARM_CTI_4_CFG_CSCTI_CFG0x4C3C02B0000x4C3C02BFFF4 KB
DEBUGSS1_ARM_CTI_5_CFG_CSCTI_CFG0x4C3C02C0000x4C3C02CFFF4 KB
DEBUGSS1_ARM_CTI_6_CFG_CSCTI_CFG0x4C3C02D0000x4C3C02DFFF4 KB
DEBUGSS1_ARM_CTI_7_CFG_CSCTI_CFG0x4C3C02E0000x4C3C02EFFF4 KB
DEBUGSS1_ARM_CTI_8_CFG_CSCTI_CFG0x4C3C02F0000x4C3C02FFFF4 KB
C66DEBUGSS0_ROM0x4C3C0300000x4C3C030FFF4 KB
C66DEBUGSS0_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG0x4C3C0340000x4C3C034FFF4 KB
C66DEBUGSS0_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG0x4C3C0350000x4C3C035FFF4 KB
C66DEBUGSS0_ARM_CTI_0_CFG_CSCTI_CFG0x4C3C0360000x4C3C036FFF4 KB
C66DEBUGSS0_ARM_CTI_1_CFG_CSCTI_CFG0x4C3C0380000x4C3C038FFF4 KB
C66DEBUGSS0_ARM_CTI_2_CFG_CSCTI_CFG0x4C3C0390000x4C3C039FFF4 KB
C66DEBUGSS0_ARM_CTI_3_CFG_CSCTI_CFG0x4C3C03A0000x4C3C03AFFF4 KB
C66DEBUGSS0_ARM_CTI_4_CFG_CSCTI_CFG0x4C3C03B0000x4C3C03BFFF4 KB
C66DEBUGSS0_ARM_CTI_5_CFG_CSCTI_CFG0x4C3C03C0000x4C3C03CFFF4 KB
C66DEBUGSS0_ARM_CTI_6_CFG_CSCTI_CFG0x4C3C03D0000x4C3C03DFFF4 KB
C66DEBUGSS0_ARM_CTI_7_CFG_CSCTI_CFG0x4C3C03E0000x4C3C03EFFF4 KB
C66DEBUGSS0_ARM_CTI_8_CFG_CSCTI_CFG0x4C3C03F0000x4C3C03FFFF4 KB
C66DEBUGSS1_ROM0x4C3C0400000x4C3C040FFF4 KB
C66DEBUGSS1_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG0x4C3C0440000x4C3C044FFF4 KB
C66DEBUGSS1_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG0x4C3C0450000x4C3C045FFF4 KB
C66DEBUGSS1_ARM_CTI_0_CFG_CSCTI_CFG0x4C3C0460000x4C3C046FFF4 KB
C66DEBUGSS1_ARM_CTI_1_CFG_CSCTI_CFG0x4C3C0480000x4C3C048FFF4 KB
C66DEBUGSS1_ARM_CTI_2_CFG_CSCTI_CFG0x4C3C0490000x4C3C049FFF4 KB
C66DEBUGSS1_ARM_CTI_3_CFG_CSCTI_CFG0x4C3C04A0000x4C3C04AFFF4 KB
C66DEBUGSS1_ARM_CTI_4_CFG_CSCTI_CFG0x4C3C04B0000x4C3C04BFFF4 KB
C66DEBUGSS1_ARM_CTI_5_CFG_CSCTI_CFG0x4C3C04C0000x4C3C04CFFF4 KB
C66DEBUGSS1_ARM_CTI_6_CFG_CSCTI_CFG0x4C3C04D0000x4C3C04DFFF4 KB
C66DEBUGSS1_ARM_CTI_7_CFG_CSCTI_CFG0x4C3C04E0000x4C3C04EFFF4 KB
C66DEBUGSS1_ARM_CTI_8_CFG_CSCTI_CFG0x4C3C04F0000x4C3C04FFFF4 KB
STM0_CXSTM0x4C3D2000000x4C3D200FFF4 KB
STM0_CTI_CSCTI0x4C3D2010000x4C3D201FFF4 KB
DEBUGSUSPENDRTR0_INTR_ROUTER_CFG0x4C3D3000000x4C3D300FFF4 KB
CPT2_AGGR0_MMR0x4C3E1000000x4C3E1000FF256 B
CPT2_AGGR0_MEM00x4C3E1200000x4C3E120FFF4 KB
CPT2_AGGR0_MEM10x4C3E1210000x4C3E121FFF4 KB
CPT2_AGGR0_MEM20x4C3E1220000x4C3E122FFF4 KB
CPT2_AGGR0_MEM30x4C3E1230000x4C3E123FFF4 KB
CPT2_AGGR0_MEM40x4C3E1240000x4C3E124FFF4 KB
CPT2_AGGR0_MEM50x4C3E1250000x4C3E125FFF4 KB
CPT2_AGGR0_MEM60x4C3E1260000x4C3E126FFF4 KB
CPT2_AGGR0_MEM70x4C3E1270000x4C3E127FFF4 KB
CPT2_AGGR0_MEM80x4C3E1280000x4C3E128FFF4 KB
CPT2_AGGR0_MEM90x4C3E1290000x4C3E129FFF4 KB
CPT2_AGGR0_MEM100x4C3E12A0000x4C3E12AFFF4 KB
CPT2_AGGR0_MEM110x4C3E12B0000x4C3E12BFFF4 KB
CPT2_AGGR0_MEM120x4C3E12C0000x4C3E12CFFF4 KB
CPT2_AGGR0_MEM130x4C3E12D0000x4C3E12DFFF4 KB
CPT2_AGGR0_MEM140x4C3E12E0000x4C3E12EFFF4 KB
CPT2_AGGR0_MEM150x4C3E12F0000x4C3E12FFFF4 KB
CPT2_AGGR0_MEM160x4C3E1300000x4C3E130FFF4 KB
CPT2_AGGR0_MEM170x4C3E1310000x4C3E131FFF4 KB
CPT2_AGGR0_MEM180x4C3E1320000x4C3E132FFF4 KB
CPT2_AGGR0_MEM190x4C3E1330000x4C3E133FFF4 KB
CPT2_AGGR0_MEM200x4C3E1340000x4C3E134FFF4 KB
CPT2_AGGR0_MEM210x4C3E1350000x4C3E135FFF4 KB
CPT2_AGGR0_MEM220x4C3E1360000x4C3E136FFF4 KB
CPT2_AGGR0_MEM230x4C3E1370000x4C3E137FFF4 KB
CPT2_AGGR0_MEM240x4C3E1380000x4C3E138FFF4 KB
CPT2_AGGR0_MEM250x4C3E1390000x4C3E139FFF4 KB
CPT2_AGGR0_MEM260x4C3E13A0000x4C3E13AFFF4 KB
CPT2_AGGR0_MEM270x4C3E13B0000x4C3E13BFFF4 KB
CPT2_AGGR0_MEM280x4C3E13C0000x4C3E13CFFF4 KB
CPT2_AGGR0_MEM290x4C3E13D0000x4C3E13DFFF4 KB
CPT2_AGGR0_MEM300x4C3E13E0000x4C3E13EFFF4 KB
CPT2_AGGR0_MEM310x4C3E13F0000x4C3E13FFFF4 KB
CPT2_AGGR1_MMR0x4C3E1400000x4C3E1400FF256 B
CPT2_AGGR1_STP2ATB_CFG0x4C3E1401000x4C3E1401FF256 B
CPT2_AGGR1_MEM00x4C3E1600000x4C3E160FFF4 KB
CPT2_AGGR1_MEM10x4C3E1610000x4C3E161FFF4 KB
CPT2_AGGR1_MEM20x4C3E1620000x4C3E162FFF4 KB
CPT2_AGGR1_MEM30x4C3E1630000x4C3E163FFF4 KB
CPT2_AGGR1_MEM40x4C3E1640000x4C3E164FFF4 KB
CPT2_AGGR1_MEM50x4C3E1650000x4C3E165FFF4 KB
CPT2_AGGR1_MEM60x4C3E1660000x4C3E166FFF4 KB
CPT2_AGGR1_MEM70x4C3E1670000x4C3E167FFF4 KB
CPT2_AGGR1_MEM80x4C3E1680000x4C3E168FFF4 KB
CPT2_AGGR1_MEM90x4C3E1690000x4C3E169FFF4 KB
CPT2_AGGR1_MEM100x4C3E16A0000x4C3E16AFFF4 KB
CPT2_AGGR1_MEM110x4C3E16B0000x4C3E16BFFF4 KB
CPT2_AGGR1_MEM120x4C3E16C0000x4C3E16CFFF4 KB
CPT2_AGGR1_MEM130x4C3E16D0000x4C3E16DFFF4 KB
CPT2_AGGR1_MEM140x4C3E16E0000x4C3E16EFFF4 KB
CPT2_AGGR1_MEM150x4C3E16F0000x4C3E16FFFF4 KB
CPT2_AGGR1_MEM160x4C3E1700000x4C3E170FFF4 KB
CPT2_AGGR1_MEM170x4C3E1710000x4C3E171FFF4 KB
CPT2_AGGR1_MEM180x4C3E1720000x4C3E172FFF4 KB
CPT2_AGGR1_MEM190x4C3E1730000x4C3E173FFF4 KB
CPT2_AGGR1_MEM200x4C3E1740000x4C3E174FFF4 KB
CPT2_AGGR1_MEM210x4C3E1750000x4C3E175FFF4 KB
CPT2_AGGR1_MEM220x4C3E1760000x4C3E176FFF4 KB
CPT2_AGGR1_MEM230x4C3E1770000x4C3E177FFF4 KB
CPT2_AGGR1_MEM240x4C3E1780000x4C3E178FFF4 KB
CPT2_AGGR1_MEM250x4C3E1790000x4C3E179FFF4 KB
CPT2_AGGR1_MEM260x4C3E17A0000x4C3E17AFFF4 KB
CPT2_AGGR1_MEM270x4C3E17B0000x4C3E17BFFF4 KB
CPT2_AGGR1_MEM280x4C3E17C0000x4C3E17CFFF4 KB
CPT2_AGGR1_MEM290x4C3E17D0000x4C3E17DFFF4 KB
CPT2_AGGR1_MEM300x4C3E17E0000x4C3E17EFFF4 KB
CPT2_AGGR1_MEM310x4C3E17F0000x4C3E17FFFF4 KB
CPT2_AGGR2_MMR0x4C3E1800000x4C3E1800FF256 B
CPT2_AGGR2_STP2ATB_CFG0x4C3E1801000x4C3E1801FF256 B
CPT2_AGGR2_MEM00x4C3E1A00000x4C3E1A0FFF4 KB
CPT2_AGGR2_MEM10x4C3E1A10000x4C3E1A1FFF4 KB
CPT2_AGGR2_MEM20x4C3E1A20000x4C3E1A2FFF4 KB
CPT2_AGGR2_MEM30x4C3E1A30000x4C3E1A3FFF4 KB
CPT2_AGGR2_MEM40x4C3E1A40000x4C3E1A4FFF4 KB
CPT2_AGGR2_MEM50x4C3E1A50000x4C3E1A5FFF4 KB
CPT2_AGGR2_MEM60x4C3E1A60000x4C3E1A6FFF4 KB
CPT2_AGGR2_MEM70x4C3E1A70000x4C3E1A7FFF4 KB
CPT2_AGGR2_MEM80x4C3E1A80000x4C3E1A8FFF4 KB
CPT2_AGGR2_MEM90x4C3E1A90000x4C3E1A9FFF4 KB
CPT2_AGGR2_MEM100x4C3E1AA0000x4C3E1AAFFF4 KB
CPT2_AGGR2_MEM110x4C3E1AB0000x4C3E1ABFFF4 KB
CPT2_AGGR2_MEM120x4C3E1AC0000x4C3E1ACFFF4 KB
CPT2_AGGR2_MEM130x4C3E1AD0000x4C3E1ADFFF4 KB
CPT2_AGGR2_MEM140x4C3E1AE0000x4C3E1AEFFF4 KB
CPT2_AGGR2_MEM150x4C3E1AF0000x4C3E1AFFFF4 KB
CPT2_AGGR2_MEM160x4C3E1B00000x4C3E1B0FFF4 KB
CPT2_AGGR2_MEM170x4C3E1B10000x4C3E1B1FFF4 KB
CPT2_AGGR2_MEM180x4C3E1B20000x4C3E1B2FFF4 KB
CPT2_AGGR2_MEM190x4C3E1B30000x4C3E1B3FFF4 KB
CPT2_AGGR2_MEM200x4C3E1B40000x4C3E1B4FFF4 KB
CPT2_AGGR2_MEM210x4C3E1B50000x4C3E1B5FFF4 KB
CPT2_AGGR2_MEM220x4C3E1B60000x4C3E1B6FFF4 KB
CPT2_AGGR2_MEM230x4C3E1B70000x4C3E1B7FFF4 KB
CPT2_AGGR2_MEM240x4C3E1B80000x4C3E1B8FFF4 KB
CPT2_AGGR2_MEM250x4C3E1B90000x4C3E1B9FFF4 KB
CPT2_AGGR2_MEM260x4C3E1BA0000x4C3E1BAFFF4 KB
CPT2_AGGR2_MEM270x4C3E1BB0000x4C3E1BBFFF4 KB
CPT2_AGGR2_MEM280x4C3E1BC0000x4C3E1BCFFF4 KB
CPT2_AGGR2_MEM290x4C3E1BD0000x4C3E1BDFFF4 KB
CPT2_AGGR2_MEM300x4C3E1BE0000x4C3E1BEFFF4 KB
CPT2_AGGR2_MEM310x4C3E1BF0000x4C3E1BFFFF4 KB
C66SS0_VBUSP_CFG_ADTF0x4C3EE000000x4C3EE003FF1 KB
C66SS1_VBUSP_CFG_ADTF0x4C3EE010000x4C3EE013FF1 KB
DEBUGSS_WRAP0_ROM_TABLE_0_10x4C400000000x4C40000FFF4 KB
DEBUGSS_WRAP0_RESV0_10x4C400010000x4C40001FFF4 KB
DEBUGSS_WRAP0_CFGAP10x4C400020000x4C400020FF256 B
DEBUGSS_WRAP0_APBAP10x4C400021000x4C400021FF256 B
DEBUGSS_WRAP0_AXIAP10x4C400022000x4C400022FF256 B
DEBUGSS_WRAP0_PWRAP10x4C400023000x4C400023FF256 B
DEBUGSS_WRAP0_PVIEW10x4C400024000x4C400024FF256 B
DEBUGSS_WRAP0_JTAGAP10x4C400025000x4C400025FF256 B
DEBUGSS_WRAP0_SECAP10x4C400026000x4C400026FF256 B
DEBUGSS_WRAP0_CORTEX0_CFG10x4C400027000x4C400027FF256 B
DEBUGSS_WRAP0_CORTEX1_CFG10x4C400028000x4C400028FF256 B
DEBUGSS_WRAP0_CORTEX2_CFG10x4C400029000x4C400029FF256 B
DEBUGSS_WRAP0_CORTEX3_CFG10x4C40002A000x4C40002AFF256 B
DEBUGSS_WRAP0_CORTEX4_CFG10x4C40002B000x4C40002BFF256 B
DEBUGSS_WRAP0_CORTEX5_CFG10x4C40002C000x4C40002CFF256 B
DEBUGSS_WRAP0_CORTEX6_CFG10x4C40002D000x4C40002DFF256 B
DEBUGSS_WRAP0_CORTEX7_CFG10x4C40002E000x4C40002EFF256 B
DEBUGSS_WRAP0_CORTEX8_CFG10x4C40002F000x4C40002FFF256 B
DEBUGSS_WRAP0_RESV1_10x4C400030000x4C40003FFF4 KB
DEBUGSS_WRAP0_RESV2_10x4C400040000x4C42003FFF32 MB
DEBUGSS_WRAP0_ROM_TABLE_1_10x4C600000000x4C60000FFF4 KB
DEBUGSS_WRAP0_CSCTI10x4C600010000x4C60001FFF4 KB
DEBUGSS_WRAP0_DRM10x4C600020000x4C60002FFF4 KB
DEBUGSS_WRAP0_RESV3_10x4C600030000x4C60003FFF4 KB
DEBUGSS_WRAP0_CSTPIU10x4C600040000x4C60004FFF4 KB
DEBUGSS_WRAP0_CTF10x4C600050000x4C60005FFF4 KB
DEBUGSS_WRAP0_RESV4_10x4C600060000x4C61005FFF16 MB
DEBUGSS_WRAP0_EXT_APB10x4C700000000x4C7FFFFFFF256 MB
COMPUTE_CLUSTER0_MSMC_PBIST0x4D100000000x4D1000FFFF64 KB
COMPUTE_CLUSTER0_A72SS0_PBIST00x4D100100000x4D1001FFFF64 KB
COMPUTE_CLUSTER0_C71SS0_PBIST0x4D100500000x4D100503FF1 KB
COMPUTE_CLUSTER0_MSMC_ECC_AGGR00x4D200000000x4D200003FF1 KB
COMPUTE_CLUSTER0_MSMC_ECC_AGGR10x4D200004000x4D200007FF1 KB
COMPUTE_CLUSTER0_MSMC_ECC_AGGR20x4D200008000x4D20000BFF1 KB
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR0x4D200100000x4D200103FF1 KB
COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR0x4D200104000x4D200107FF1 KB
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR0x4D200108000x4D20010BFF1 KB
COMPUTE_CLUSTER0_C71SS0_ECC_AGGR0x4D200500000x4D200503FF1 KB
COMPUTE_CLUSTER0_ECC_AGGR_CTL0x4D200B00000x4D200B03FF1 KB
COMPUTE_CLUSTER0_ECC_AGGR_VBUS0x4D200B04000x4D200B07FF1 KB
COMPUTE_CLUSTER0_ECC_AGGR_CFG0x4D200B08000x4D200B0BFF1 KB
COMPUTE_CLUSTER0_ECC_AGGR0x4D200C00000x4D200C03FF1 KB
COMPUTE_CLUSTER0_CC_REGS0x4D210000000x4D2100FFFF64 KB
C66SS0_VBUSP_CFG_PBISTCFG0x4D800000000x4D8000FFFF64 KB
C66SS0_C66_SDMA_L2SRAM_00x4D808000000x4D8083FFFF256 KB
C66SS0_C66_SDMA_L1DSRAM0x4D80F000000x4D80F07FFF32 KB
C66SS1_VBUSP_CFG_PBISTCFG0x4D810000000x4D8100FFFF64 KB
C66SS1_C66_SDMA_L2SRAM_00x4D818000000x4D8183FFFF256 KB
C66SS1_C66_SDMA_L1DSRAM0x4D81F000000x4D81F07FFF32 KB
R5FSS0_CORE0_ICACHE0x4E000000000x4E007FFFFF8 MB
R5FSS0_CORE0_DCACHE0x4E008000000x4E00FFFFFF8 MB
R5FSS0_CORE1_ICACHE0x4E010000000x4E017FFFFF8 MB
R5FSS0_CORE1_DCACHE0x4E018000000x4E01FFFFFF8 MB
R5FSS1_CORE0_ICACHE0x4E100000000x4E107FFFFF8 MB
R5FSS1_CORE0_DCACHE0x4E108000000x4E10FFFFFF8 MB
R5FSS1_CORE1_ICACHE0x4E110000000x4E117FFFFF8 MB
R5FSS1_CORE1_DCACHE0x4E118000000x4E11FFFFFF8 MB
VPAC0_VPAC_TOP_PAC_BASE_MEM_SLV_CBASS_STRIPE_MSRAM_SLV0x4F000000000x4F0007FFFF512 KB
DMPAC0_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_MEM_SLV_CBASS_STRIPE_MSRAM_SLV0x4F010000000x4F0107FFFF512 KB
(1) These regions are used when R5FSS0 and R5FSS1 work in split mode. For more information about split and lockstep modes, see Section 6.3.3.2 MCU Cortex-R5F Core. For more information about ATCM and BTCM, see Section 6.3.3.2.2 Tightly-Coupled Memories (TCMs).
Table 2-2 NAVSS0 Alias Memory Map
Note:

NAVSS0_DDR0 and NAVSS0_DDR1 are used for load balancing and real time/ non-real time traffic separation. Max addressable DDR memory across the two paths is 8 GB.