SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
In order to initialize the TBL RAMs for ECC codes, there must be no transactions to the TBU for at least 32 TBU clock cycles after reset while the RAM is busy. During this time the software must not enable any IOs for SMMU usage.