SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
This section describes the DPHY_TX integration in the device MAIN domain, including information about clocks and resets.
There is one DPHY_TX integrated in the device MAIN domain - DPHY_TX0. Figure 12-1176 shows the integration of DPHY_TX.
Table 12-1551 and Table 12-1552 summarize the integration of DPHY_TX in device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
DPHY_TX0 | PSC0 | PD2 | LPSC57 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
DPHY_TX0 | DPHY_TX0_CLK | SYSCLK0 / 4 | PLLCTRL0 | DPHY_TX0 interface clock |
PSM_CLK | PLL1_HSDIV8_CLKOUT | PLL1_HSDIV8 | DPHY_TX0 reference clock | |
IP1_PPI_K_M_TXCLKESC | DPHY_TX0 escape mode clock | |||
IP1_PPI_K_LN0_M_TXCLKESC | DPHY_TX0 escape mode clock for lane 0 for IP1_PPI | |||
IP1_PPI_K_LN1_M_TXCLKESC | DPHY_TX0 escape mode clock for lane 1 for IP1_PPI | |||
IP1_PPI_K_LN2_M_TXCLKESC | DPHY_TX0 escape mode clock for lane 2 for IP1_PPI | |||
IP1_PPI_K_LN3_M_TXCLKESC | DPHY_TX0 escape mode clock for lane 3 for IP1_PPI | |||
DPHY_REF_CLK | HFOSC0_CLKOUT | HFOSC0 | DPHY_TX0 reference clock. The selection of the source clock (see , DPHY_TX Integration) is provided via the CTRLMMR_DPHY0_CLKSEL[1:0] REF_CLK_SEL register bit-field in device Control Module. | |
HFOSC1_CLKOUT | HFOSC1 | |||
MAIN_PLL3_HSDIV4_CLKOUT | MAIN_PLL3_HSDIV4 | |||
MAIN_PLL2_HSDIV4_CLKOUT | MAIN_PLL2_HSDIV4 | |||
DSI0 | PPI_0_TXBYTECLKHS | IP1_PPI_C_TXBYTECLKHS | DPHY_TX0 | DPHY_TX0 byte clock for IP1_PPI |
DPHY_0_RXCLKESC | IP1_PPI_K_LN0_M_RXCLKESC | DPHY_TX0 reverse escape mode recovered clock from lane 0 | ||
CSI_TX_IF0 | DPHY_TXBYTECLKHS | IP2_PPI_C_TXBYTECLKHS | DPHY_TX0 | DPHY_TX0 byte clock for IP2_PPI |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
DPHY_TX0 | DPHY_TX0_RST | MOD_G_RST | LPSC57 | DPHY_TX0 reset |