SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
The address slice transfers address information between the DDR controller and the SDRAM devices and contains 6 address bits.
The address write data path logic (from DFI to pads) and the read data path logic (loopback only) are contained within the address slice. Termination and directional controls for the address path related I/Os also exist in this slice.