SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Although containing some of the basic external components, Figure 5-11 to Figure 12-210 must not be considered as an exhaustive guide for the PCB designer. TI provides additional documents for those who are willing to design PCBs and/or fine tune the SerDes.
Figure 12-207 shows the I/O interface pins of SerDes.
Table 12-259 describes the external signals of SERDES0 module.
Device Pin | Module Signal | I/O(1) | Description | Value at Reset |
---|---|---|---|---|
SERDES0_RX0_P | RX_P_LN0 | I | SerDes differential data receive pins. Lane 0 | HiZ |
SERDES0_RX0_N | RX_M_LN0 | |||
SERDES0_TX0_P | TX_P_LN0 | O | SerDes differential data transmit pins. Lane 0 | HiZ |
SERDES0_TX0_N | TX_M_LN0 | |||
SERDES0_RX1_P | RX_P_LN1 | I | SerDes differential data receive pins. Lane 1 | HiZ |
SERDES0_RX1_N | RX_M_LN1 | |||
SERDES0_TX1_P | TX_P_LN1 | O | SerDes differential data transmit pins. Lane 1 | HiZ |
SERDES0_TX1_N | TX_M_LN1 | |||
PCIE_REFCLK0P | CMN_REFCLK1_P | I | SerDes external system reference clock for PCIe | HiZ |
PCIE_REFCLK0N | CMN_REFCLK1_M | |||
SERDES0_CMN_REFCLK_DER | O | SerDes system reference clock for external PCIe device. Selected via CTRLMMR_PCIE_REFCLK0_CLKSEL | ||
SERDES1_CMN_REFCLK_DER | ||||
SERDES0_CMN_REFCLK1 | ||||
SERDES1_CMN_REFCLK1 | ||||
SERDES0_REXT | CMN_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. | HiZ |
Figure 12-208 shows the I/O interface pins of SerDes.
Table 12-260 describes the external signals of SERDES1 module.
Device Pin | Module Signal | I/O | Description | Value at Reset |
---|---|---|---|---|
SERDES1_RX0_P | RX_P_LN0 | I | SerDes differential data receive pins. Lane 0 | HiZ |
SERDES1_RX0_N | RX_M_LN0 | |||
SERDES1_TX0_P | TX_P_LN0 | O | SerDes differential data transmit pins. Lane 0 | HiZ |
SERDES1_TX0_N | TX_M_LN0 | |||
SERDES1_RX1_P | RX_P_LN1 | I | SerDes differential data receive pins. Lane 1 | HiZ |
SERDES1_RX1_N | RX_M_LN1 | |||
SERDES1_TX1_P | TX_P_LN1 | O | SerDes differential data transmit pins. Lane 1 | HiZ |
SERDES1_TX1_N | TX_M_LN1 | |||
PCIE_REFCLK1P | CMN_REFCLK1_P | I | SerDes external system reference clock for PCIe | HiZ |
PCIE_REFCLK1N | CMN_REFCLK1_M | |||
SERDES0_CMN_REFCLK_DER | O | SerDes system reference clock for external PCIe device. Selected via CTRLMMR_PCIE_REFCLK1_CLKSEL | ||
SERDES1_CMN_REFCLK_DER | ||||
SERDES0_CMN_REFCLK1 | ||||
SERDES1_CMN_REFCLK1 | ||||
SERDES1_REXT | CMN_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. | HiZ |
Figure 12-209 shows the I/O interface pins of SerDes.
Table 12-261 describes the external signals of SERDES2 module.
Device Pin | Module Signal | I/O | Description | Value at Reset |
---|---|---|---|---|
SERDES2_RX0_P | RX_P_LN0 | I | SerDes differential data receive pins. Lane 0 | HiZ |
SERDES2_RX0_N | RX_M_LN0 | |||
SERDES2_TX0_P | TX_P_LN0 | O | SerDes differential data transmit pins. Lane 0 | HiZ |
SERDES2_TX0_N | TX_M_LN0 | |||
SERDES2_RX1_P | RX_P_LN1 | I | SerDes differential data receive pins. Lane 1 | HiZ |
SERDES2_RX1_N | RX_M_LN1 | |||
SERDES2_TX1_P | TX_P_LN1 | O | SerDes differential data transmit pins. Lane 1 | HiZ |
SERDES2_TX1_N | TX_M_LN1 | |||
PCIE_REFCLK2P | CMN_REFCLK1_P | I | SerDes external system reference clock for PCIe | HiZ |
PCIE_REFCLK2N | CMN_REFCLK1_M | |||
SERDES2_CMN_REFCLK_DER | O | SerDes system reference clock for external PCIe device. Selected via CTRLMMR_PCIE_REFCLK2_CLKSEL | ||
SERDES3_CMN_REFCLK_DER | ||||
SERDES2_CMN_REFCLK1 | ||||
SERDES3_CMN_REFCLK1 | ||||
SERDES2_REXT | CMN_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. | HiZ |
Figure 12-210 shows the I/O interface pins of SerDes.
Table 12-262 describes the external signals of SERDES3 module.
Device Pin | Module Signal | I/O | Description | Value at Reset |
---|---|---|---|---|
SERDES3_RX0_P | RX_P_LN0 | I | SerDes differential data receive pins. Lane 0 | HiZ |
SERDES3_RX0_N | RX_M_LN0 | |||
SERDES3_TX0_P | TX_P_LN0 | O | SerDes differential data transmit pins. Lane 0 | HiZ |
SERDES3_TX0_N | TX_M_LN0 | |||
SERDES3_RX1_P | RX_P_LN1 | I | SerDes differential data receive pins. Lane 1 | HiZ |
SERDES3_RX1_N | RX_M_LN1 | |||
SERDES3_TX1_P | TX_P_LN1 | O | SerDes differential data transmit pins. Lane 1 | HiZ |
SERDES3_TX1_N | TX_M_LN1 | |||
PCIE_REFCLK3P | CMN_REFCLK1_P | I | SerDes external system reference clock for PCIe | HiZ |
PCIE_REFCLK3N | CMN_REFCLK1_M | |||
SERDES2_CMN_REFCLK_DER | O | SerDes system reference clock for external PCIe device. Selected via CTRLMMR_PCIE_REFCLK3_CLKSEL | ||
SERDES3_CMN_REFCLK_DER | ||||
SERDES2_CMN_REFCLK1 | ||||
SERDES3_CMN_REFCLK1 | ||||
SERDES3_REXT | CMN_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. | HiZ |