SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Figure 1-1 shows the integration of the PDMA modules in the device MAIN domain.
Table 10-172 through Table 10-174 summarize the integration of the PDMA modules in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
PDMA0 (PDMA_AASRC) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA2 (PDMA_DEBUG_CCMCU) | PSC0 | PD0 | LPSC13 | CBASS0 |
PDMA3 (PDMA_DEBUG_C66) | PSC0 | PD0 | LPSC13 | CBASS0 |
PDMA5 (PDMA_MCAN) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA6 (PDMA_MCASP_G0) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA7 (PDMA_MCASP_G1) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA8 (PDMA_MISC_G0) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA9 (PDMA_MISC_G1) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA10 (PDMA_MISC_G2) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA11 (PDMA_MISC_G3) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA13 (PDMA_USART_G0) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA14 (PDMA_USART_G1) | PSC0 | PD0 | LPSC0 | CBASS0 |
PDMA15 (PDMA_USART_G2) | PSC0 | PD0 | LPSC0 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
PDMA0 | PDMA0_FICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | PDMA0 functional and interface clock |
PDMA2 | PDMA2_FICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | PDMA2 functional and interface clock |
PDMA3 | PDMA3_FICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | PDMA3 functional and interface clock |
PDMA5 | PDMA5_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA5 functional and interface clock |
PDMA6 | PDMA6_FICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | PDMA6 functional and interface clock |
PDMA7 | PDMA7_FICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | PDMA7 functional and interface clock |
PDMA8 | PDMA8_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA8 functional and interface clock |
PDMA9 | PDMA9_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA9 functional and interface clock |
PDMA10 | PDMA10_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA10 functional and interface clock |
PDMA11 | PDMA11_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA11 functional and interface clock |
PDMA13 | PDMA13_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA13 functional and interface clock |
PDMA14 | PDMA14_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA14 functional and interface clock |
PDMA15 | PDMA15_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | PDMA15 functional and interface clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
PDMA0 | PDMA0_RST | MOD_G_RST | LPSC0 | PDMA0 hardware reset |
PDMA2 | PDMA2_RST | MOD_G_RST | LPSC13 | PDMA2 hardware reset |
PDMA3 | PDMA3_RST | MOD_G_RST | LPSC13 | PDMA3 hardware reset |
PDMA5 | PDMA5_RST | MOD_G_RST | LPSC0 | PDMA5 hardware reset |
PDMA6 | PDMA6_RST | MOD_G_RST | LPSC0 | PDMA6 hardware reset |
PDMA7 | PDMA7_RST | MOD_G_RST | LPSC0 | PDMA7 hardware reset |
PDMA8 | PDMA8_RST | MOD_G_RST | LPSC0 | PDMA8 hardware reset |
PDMA9 | PDMA9_RST | MOD_G_RST | LPSC0 | PDMA9 hardware reset |
PDMA10 | PDMA10_RST | MOD_G_RST | LPSC0 | PDMA10 hardware reset |
PDMA11 | PDMA11_RST | MOD_G_RST | LPSC0 | PDMA11 hardware reset |
PDMA13 | PDMA13_RST | MOD_G_RST | LPSC0 | PDMA13 hardware reset |
PDMA14 | PDMA14_RST | MOD_G_RST | LPSC0 | PDMA14 hardware reset |
PDMA15 | PDMA15_RST | MOD_G_RST | LPSC0 | PDMA15 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
PDMA5 | PDMA5_ECC_SEC_PEND | ESM0_LVL_IN_120 | ESM0 | PDMA5 SEC ECC error interrupt | Level |
PDMA5_ECC_DED_PEND | ESM0_LVL_IN_121 | ESM0 | PDMA5 DED ECC error interrupt | Level |