SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
The module supports a number of channels (see Section 8.3.2.1.2), each having its own independent TLB and translation entries. This allows a single PVU to handle the translations for many masters, as well as keep their translations from interfering with each other.
The mapping of transactions to TLBs is made using mapping registers (PVU_VIRTID_MAP1 and PVU_VIRTID_MAP2). Each channel can be mapped to a virtID, or as a sub range of a DMA virtID. This allows the software to decide how the transactions are mapped to TLBs. It can be purely based on virtID, so that each virtual space has its own TLB. Or, it can be partly based on a highly channelized master, such as a DMA, can have 4 TLBs dedicated for channels where the sub-class on the upper chanid bits determine which of the 4 TLBs to use. This DMA mode allows for different classes of DMA traffic, such as descriptors or buffers, to be in their own TLBs and not interfere with each other. Since the TLB mapping is relatively simple, it is software's responsibility to control the definition of virtIDs in peripherals and DMAs so that they map to TLBs as required.