SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
A total of N destination channels are provided within the PDMA for concurrent transfers from Tx per-channel buffers to the various attached peripherals, where N is a design-time configurable paramater. Each Tx channel requires a single PSI-L thread. See Section 10.3.2 for Tx channel allocation for each PDMA.