NAVSS0_UDMAP0 controller module supports the following modes and features:
- TI K3 DMA Architecture compliant Tx/Rx port implementation (see Section 10.1, DMA Architecture)
- Implements TI DMA Architecture-compliant Packet-Oriented DMA Functionality (UDMA-P)
- Provides internal Tx Packet Oriented DMA processing unit
- Provides internal Rx Packet Oriented DMA processing unit
- Supports rflow_cnt unique Rx flow table entries
- Supports 1 transmit queue per data connection
- Supports 1 receive queue per data connection
- Supports physical separation of buffer control and payload information
- Supports host and monolithic descriptor formats
- Supports unlimited buffer scatter/gather for packets using host descriptor type
- Supports data buffer sizes up to 4 Mbytes
- Supports variable first valid byte offset within data buffers
- Supports packet truncation on transmit
- Provides per-channel buffering:
- Provides 16 word deep × 128-bit Packet FIFO for each Tx channel
- Provides 4 word deep Packet Info FIFO for each Rx channel
- Provides 8 word deep × 128-bit Packet Data FIFO for each Rx channel
- Supports up to 32 Protocol Specific words for Tx packets
- Supports up to 32 Protocol Specific words for Rx packets
- Implements TI DMA Architecture compliant Third Party Channel Controller
- Channel controller is built as a prefetcher engine
- Provides the same functionality as a discrete UDMA-C/UTC combination
- Provides a fully integrated TI DMA Architecture Third Party DMA compliant solution
- Can also fetch TRs and writeback TR responses for up to echan_cnt external channels which are transported via the TR PSI-L interface
- Implements TI DMA Architecture compliant Unified Transfer Controller
- Provides a memory read access unit
- Supports read bursts up to 128 bytes (limited by Tx Per Channel FIFO depth for the channel)
- Provides a memory write access unit
- Supports write bursts up to 128 bytes (limited by Tx Per Channel FIFO depth for the channel)
- Supports Type 0-4, and Type 15 Transfer Request types
- Provides a set of TI DMA Architecture compliant Unified DMA channels which all share the execution hardware using time division multiplexing
- Supports tchan_cnt concurrent Tx channels
- Each Tx channel can be configured at runtime to be:
- Packet oriented Tx data channel
- Third party combination source control and data channel (Third Party channel mode)
- Supports rchan_cnt simultaneous Rx (destination) channels
- Each Rx channel can be configured at runtime to be:
- Packet oriented Rx data channel
- Third party combination destination control and data channel (Third Party channel mode)
- Provides support for three different groups of
internal channels:
- Ultra-high
capacity (UHC) channels
- Quantity
specified by: uchan_cnt
- Provide
deeper Tx Per Channel FIFOs
- Provide
16 deep descriptor/TR prefetch buffers
- UHC
channels are the first uchan_cnt channels within
the Tx and Rx arrays (starting with channel 0 and
extending up to channel uchan_cnt-1)
- Tx and Rx
UHC channels are specified as a matched pair
- Still usable as split channels but design must
have same number of Tx/Rx UHC channels
- High-capacity
(HC) channels:
- Quantity
specified by: hchan_cnt - uchan_cnt
- Provide
deeper Tx Per Channel FIFOs
- Provide
16 deep descriptor/TR prefetch buffers
- HC
channels are the next hchan_cnt channels (after
any UHC channels) within the Tx and Rx channel arrays
(starting with channel uchan_cnt and extending up
to uchan_cnt + hchan_cnt-1).
- Normal capacity
(NC) channels:
- Quantity
on Tx specified by: tchan_cnt - uchan_cnt -
hchan_cnt
- Quantity
on Rx specified by: rchan_cnt - uchan_cnt -
hchan_cnt
- Provide
standard depth Tx/Rx per channel FIFOs
- Provide 1
deep descriptor/TR prefetch buffers
Note:
User can
still use ultra-high capacity and high-capacity channels
as general normal-capacity channels though may not be
taking advantage of the potential DMA throughput
advantages.
- Provides per-channel buffering:
- Provides 16 word deep data FIFO for each NC Tx (source) channel
- Provides 8 word deep data FIFO for each NC Rx (destination) channel
- Provides single 128-bit read/write VBUSM master interface for prefetcher accesses to RINGACC and memory.
- Supports up to 16 outstanding reads.
- Supports up to 16 outstanding writes.
- Provides single 128-bit read/write VBUSM master interface for packet DMA and coherency unit accesses to RINGACC and memory.
- Supports up to 16 outstanding reads.
- Supports up to 16 outstanding writes.
- Provides single 128-bit read only VBUSM master interface for payload transfers.
- Supports up to 16 outstanding reads.
- Provides single 128-bit write only VBUSM master interface for payload transfers.
- Supports up to 16 outstanding writes.
- Provides 128-bit wide PSI-L compliant source interface for sending data to remote UTCs and remote peripherals
- Includes 1 outgoing event transport lane
- Provides 128-bit wide PSI-L compliant destination interface for receiving data from remote UTCs and remote peripherals
- Includes 1 incoming event transport lane
- Provides PSI-L interface for sending Transfer Requests to remote UTC channels and receiving back Transfer Responses
- Provides 32 entry deep unified Transfer Response FIFO for external channels
- Provides 0 local event input buses