SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
The DDR controller has a BIST engine that supports MOVI3N and limited MOVI algorithms, a self-refresh retention test, an idle retention test and a memory initialization test for detecting the following faults:
The DDR controller also supports BIST on ECC lanes for out-of-band ECC configuration. The following are the BIST related registers: