SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
A module can be in one of the following states: Disable, Enable, SwRstDisable, or SyncRst. As shown in Table 5-69, these states correspond to combinations of module reset asserted or de-asserted and module clock on or off. Note that module reset is defined as to a full reset of a given module, such that all hardware is put back into its default state.
Module State | Module Reset | Module Clock | Disabled Request to Interconnect | VBUS Request |
---|---|---|---|---|
Disable | De-asserted | OFF | Asserted | Re-directed to Infrastructure NULL endpoint. |
Enable | De-asserted | ON | De-asserted | VBUS requests are served. |
SwRstDisable | Asserted | OFF | Asserted | Re-directed to Infrastructure NULL endpoint. |
SyncRst | Asserted | ON | Asserted | Re-directed to Infrastructure NULL endpoint. |