SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
The DISPC is capable of reading a compressed frame buffer through the FBDC block. The FBDC is a Frame Buffer Decompression module that is compatible with the lossless compression module (FBC) in the GPU in the SoC. The FBDC performs the lossless decompression of the compressed images on a tile-by-tile basis. The size of the tiles is 16 pixels by 4 lines or 32 pixels by 2 lines. The FBDC is enabled by setting the DSS0_VID_FBDC_ATTRIBUTES[0] ENABLE register bit.