SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
CLEC output events can be routed to SoC, DRU or C71/A72 corepacs. For Soc, DRU, and ARM events, the exact event number mapping is controlled by the CLEC_MRR_j[15-8] EXT_EVNUM bit field. For C71 events, the exact event number mapping is controlled by the CLEC_MRR_j[5-0] C7X_EVNUM bit field.
Table 9-10 shows the CLEC output event map.
Destination | Event Number | Register Setting | Triggered Event |
---|---|---|---|
SoC | 127-0 | CLEC_MRR_j[15-8] EXT_EVNUM | SoC output events |
DRU | 159-128 | CLEC_MRR_j[15-8] EXT_EVNUM | DRU local input trigger events |
Reserved | 191-160 | Reserved | Reserved |
A72 corepac | 192 | CLEC_MRR_j[15-8] EXT_EVNUM | A72 event for intra-core synchronization with C71 |
Reserved | 255-193 | Reserved | Reserved |
C71 corepac | 63-0 | CLEC_MRR_j[5-0] C7x_EVNUM | C71SS events |