The L2 memory system provides the following key features:
- L2 unified memory controller (UMC) with 512KB L2 memory, configurable as cache and/or SRAM
- L2 cache
- 8-way set-associative
- 128-byte cache line size
- Write-allocate cache
- Support for both write-back and write-through modes
- Physically indexed, physically tagged (40-bit physical address)
- Supports 2×64-byte streams from one streaming engine
- External MMR and MDMA accesses on an unified interface to MSMC
- Caches MMU page tables
- Cache pre-warming from SE and/or MSMC
- L2 SRAM
- Security firewall on L2 SRAM accesses
- DMA access to L2 SRAM on merged MSMC I/F
- Bandwidth
- 2048-bit data throughput (see Section 6.5.3.4, C71x DSP Streaming Engine)
- 4×512-bit banks, with 2 virtual banks each
- ECC SECDED support
- Coherence
- Full MESI support
- Support for global coherence operations
- Snoops for L2 SRAM, MSMC SRAM and external (DDR) addresses
- User coherence commands from SE
- Full coherence between L1D cache, SE, L2 SRAM, MSMC SRAM and DDR
- ECR access
- L2 ECR registers are not memory mapped and instead are mapped to a MOVC CPU instruction