SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Table 5-122 lists the operating frequency ranges for the system clocks of the device.
| System Clocks | Minimum Operating Frequency (MHz) |
|---|---|
| MCU_PLL0 (MCU TBD PLL) with WKUP_PLLCTRL0 | TBD |
| MCU_PLL1 (MCU PERIPHERAL PLL) | TBD |
| MCU_PLL2 (MCU CPSW PLL) | TBD |
| PLL0 (MAIN PLL) with PLLCTRL0 | TBD |
| PLL1 (PER0 PLL) | TBD |
| PLL2 (PER1 PLL) | TBD |
| PLL3 (CPSW9G PLL) | TBD |
| PLL4 (AUDIO0 PLL) | TBD |
| PLL5 (VIDEO PLL) | TBD |
| PLL6 (GPU PLL) | TBD |
| PLL7 (C7x PLL) | TBD |
| PLL8 (ARM0 PLL) | TBD |
| PLL12 (DDR PLL) | TBD |
| PLL13 (C66 PLL) | TBD |
| PLL14 (PULSAR PLL) | TBD |
| PLL15 (AUDIO1 PLL) | TBD |
| PLL16 (DSS PLL0) | TBD |
| PLL17 (DSS PLL1) | TBD |
| PLL18 (DSS PLL2) | TBD |
| PLL19 (DSS PLL3) | TBD |
| PLL23 (DSS PLL7) | TBD |
| PLL24 (MLB PLL) | TBD |
| PLL25 (VISION PLL) | TBD |
(1) Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only.
(2) Interconnect clock on DSS is CPU/4. This will range from 100 MHz to 250 MHz.
(3) When Main PLL is configured to 400 MHz mode, DSS can only support a max pixel clock of 74.25 MHz. For lower resolution displays the DSS clock can be lower than 74.25 MHz.