SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

6.2.3.6.4 Example of Using RAT to Access Full 36b SoC Memory Map

This section shows an example on how to utilize RAT block to allow R5 to access 36 SoC Memory Map. The RAT block inside R5 has up to 8 address remapping regions.

Assuming R5 needs to access the following region:

All the SoC level on-chip SRAM
All the SoC level peripherals
Access 512MB OSPI region at address 0x4_0000_0000
Access 1GB DDR region at address 0x9_0000_0000
Access 512MB DDR region at address 0x8000_0000

First of all, we need to construct 32b R5 memory map as following and how those memory spaces are mapped to SoC level, shown in Table 6-118. Users can define where the OSPI and DDR data space placed inside R5’s memory map and how they should be mapped to SoC level address map. Table 6-118 just shows one of the many possible ways to construct the memory map.

Table 6-118 Example of R5 Address Mapping

	R5 Memory Map(32b)	SoC Memory Map (36b)	RAT Remapping
SoC Level peripheral and on-chip SRAM (This is guaranteed by SoC Hardware design. No user configuration is needed)	0x0 to 0x7FFF_FFFF Same address as SoC memory map	0x0 to 0x7FFF_FFFF	Not RAT Remapping
512MB OSPI data region (user defined)	0x8000_0000 to 0x9FFF_FFFF	0x4_0000_0000 to 0x4_1FFF_FFFF	Using RAT remapping region 0
512MB DDR space (user defined)	0xA000_0000 to 0xBFFF_FFFF	0x8000_0000 to 0x9FFF_FFFF	Using RAT remapping region 1
Additional 1GB DDR Space (user defined)	0xC000_0000 to 0xFFFF_FFFF	0x9_0000_0000 to 0x9_3FFF_FFFF	Using RAT remapping region 2

In this example, only three RAT regions are needed:

Region 0 is used to remap R5’s address between 0x8000_0000 to 0x9FFF_FFFF to SoC level address 0x4_0000_0000 to 0x4_1FFF_FFFF
Region 1 is used to remap R5’s address between 0xA000_0000 to 0xBFFF_FFFF to 0x8000_0000 to 0x9FFF_FFFF
Region 2 is used to remap R5’s address 0xc000_0000 t0 0xFFFF_FFFF to 0x9_0000_0000 to 0x9_3FFF_FFFF.

In order achieving those mappings, those are the setting of the RAT configuration registers:

	Region 0	Region 1	Region 2	Other regions
Region control register	Enabled, size set to 512MB	Enabled, size set to 512MB	Enabled, size set to 1GB	disabled
Region base(32b)	0x8000_0000	0xA000_0000	0xc000_0000	Don’t care
Region translated lower address(32b)	0x0000_0000	0x8000_0000	0x0000_0000	Don’t care
Region translated upper address	0x4	0x0	0x9	Don’t care

Figure 6-59 shows how RAT is remapping the address between R5’s 32b address to 36b SoC address.

Figure 6-59 RAT Configuration Example