During synchronous accesses with WAIT pin
monitoring enabled (the GPMC_CONFIG1_i[21] WAITWRITEMONITORING bit), the WAIT pin is
captured synchronously with GPMC output clock, using the rising edge of this
clock.
If enabled, external WAIT pin monitoring can be used in combination with WRACCESSTIME to delay the GPMC output clock capture edge of the effective memory device.
WAIT-monitoring pipelining depth is similar to synchronous read access:
- At WRACCESSTIME completion if WAITMONITORINGTIME = 0
- In the WAITMONITORINGTIME x (GPMCFCLKDIVIDER + 1) GPMC_FCLK cycles before WRACCESSTIME completion if WAITMONITORINGTIME is not equal to 0
Wait-monitoring pipelining definition applies to whole burst accesses:
- Wait monitored as active freezes the CYCLETIME counter. For accesses within a burst, when the CYCLETIME counter is by definition in a lock state, wait monitored as active indicates that the data bus is not being captured by the external device. Control signals are kept in their current state. The data bus is kept in its current state.
- Wait monitored as inactive unfreezes the CYCLETIME counter. For accesses within a burst, when the CYCLETIME counter is by definition in a lock state, wait monitored as inactive indicates the effective data capture of the bus by the external device and starts the next access of the burst. In case of a single access or if this was the last access in a multiple access cycle, all signals, including the data bus, are controlled according to their related control timing value and the CYCLETIME counter status.
Note: WAIT monitoring is supported for all
configurations except GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME = 0x0 (where i =
0 to 3) for write bursts with a clock divider of 1 or 2 (the GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER bit field is equal to 0x0 or 0x1, respectively).