When an FIQ interrupt is received, the CPU should follow these steps:
- Read the R5FSS_VIM_FIQVEC register and jump to that address to service the ISR
- Reading this register will mask (discard) all interrupts of an equal or lower priority and de-assert the coreN_FIQn output. If another interrupt of a higher priority becomes available, the coreN_FIQn will re-assert, allowing priority interruption of an interrupt.
- Reading this register will cause the value from the R5FSS_VIM_PRIFIQ[9:0] NUM bit field to be loaded into the R5FSS_VIM_ACTFIQ[9:0] NUM bit field, and the R5FSS_VIM_ACTFIQ[31] VALID bit to be set
- Service the interrupt
- Depending on whether the original source of the interrupt was a pulse or a level (determined by reading the R5FSS_VIM_ACTFIQ[9:0] NUM bit field to determine number, and reading the appropriate bit in the R5FSS_VIM_INTTYPE_j register to determine type)
- Pulse
- Clear the status by writing a '1' to the appropriate bit in the R5FSS_VIM_STS_j register, or R5FSS_VIM_FIQSTS_j register
- Clear the interrupt at the source. This way, the source can generate another pulse, if it needs to, and the VIM will process this as a new interrupt
- Level
- Clear the interrupt at the source
- Clear the status by writing a '1' to the appropriate bit in the R5FSS_VIM_STS_j register, or R5FSS_VIM_FIQSTS_j register. This way, the level should be gone at the input to the VIM, it will avoid falsely re-calling the interrupt. If the source maintains the level, then it means there is another interrupt
- Write any value to the R5FSS_VIM_FIQVEC register
- This will clear the priority mask and will cause all interrupts to be re-evaluated for the new highest priority interrupt
- This will also clear the R5FSS_VIM_ACTFIQ[31] VALID bit