SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

6.4.8.2.4 PRU_ICSSG UART Clock Generation and Control

The PRU_ICSSG UART0 bit clock is derived from an input clock to the PRU_ICSSG UART0. See the device-specific Datasheet to check the maximum data rate supported by the PRU_ICSSG UART0.

Figure 6-223 is a conceptual clock generation diagram for the PRU_ICSSG UART0. The processor clock generator receives a signal from an external clock source and produces a PRU_ICSSG UART0 input clock with a programmed frequency. The PRU_ICSSG UART0 contains a programmable baud generator that takes an input clock and divides it by a divisor in the range between 1 and (2¹⁶ - 1) to produce a baud clock (BCLK). The frequency of BCLK is sixteen times (16×) the baud rate (each received or transmitted bit lasts 16 BCLK cycles) or thirteen times (13×) the baud rate (each received or transmitted bit lasts 13 BCLK cycles). When the PRU_ICSSG UART0 is receiving, the bit is sampled in the 8th BCLK cycle for 16× over sampling mode and on the 6th BCLK cycle for 13× over-sampling mode. The 16× or 13× reference clock is selected by configuring the mode definition register: UART_MODE[0] OSM_SEL bit. The formula to calculate the divisor is:

Two 8-bit register fields:

UART_DIVMSB[7-0] DLH
UART_DIVLSB[7-0] DLL,

called divisor latches, hold this 16-bit divisor. DLH holds the most significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about these register fields, see the PRU_ICSSG UART0 register descriptions in the PRU_UART_UART0 Registers. These divisor latches must be loaded during initialization of the PRU_ICSSG UART0 in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value.

Figure 6-224 summarizes the relationship between the transferred data bit, BCLK, and the PRU_ICSSG UART0 input clock. Note that the timing relationship depicted in Figure 6-224 shows that each bit lasts for 16 BCLK cycles. This is in case of 16x over-sampling mode. For 13× over-sampling mode each bit lasts for 13 BCLK cycles.

Example baud rates and divisor values relative to a 150 MHz PRU_ICSSG UART0 input clock and 16× over-sampling mode are shown in Table 6-460.

Figure 6-223 PRU_ICSSG UART Clock Generation Diagram

Figure 6-224 Relationships Between PRU_ICSSG UART Data Bit, BCLK, and Input Clock

Table 6-460 Baud Rate Examples for 192-MHZ PRU_ICSSG UART Input Clock and 16× Over-sampling Mode

Baud Rate	Divisor Value	Actual Baud Rate	Error (%)
2400	5000	2400	0.00
4800	2500	4800	0.00
9600	1250	9600	0.00
19200	625	19200	0.00
38400	313	38338.658	–0.16
56000	214	56074.766	0.13
115200	104	115384.6	0.16
128000	94	127659.574	–0.27
3000000	4	3000000	0.00
6000000	2	3000000	0.00
12000000	1	12000000	0.00

Table 6-461 Baud Rate Examples for 192-MHZ PRU_ICSSG UART Input Clock and 13× Over-sampling Mode

Baud Rate	Divisor Value	Actual Baud Rate	Error (%)
2400	6154	2399.940	–0.0025
4800	3077	4799.880	–0.0025
9600	1538	9602.881	0.03
19200	769	19205.762	0.03
38400	385	38361.638	–0.10
56000	264	55944.056	–0.10
115200	128	115384.6	0.16
128000	115	128428.094	0.33