The 3 channel Peripheral Interface supports functionality for operations utilizing the EnDat 2.2 and BiSS protocols.
This module supports the following features:
- 3 channels with baud range from 100 kHz to 16 MHz
- ICSSGn_UART_CLK (default) or ICSSGn_ICLK controller clock is an
input to independent div16fr clock dividers to produce a 1X clock
(PERIF<m>_CLK) and oversampling clock
- Half-duplex (TX and RX are not supported concurrently)
- TX FIFO size of 32 bits
- RX FIFO size of 4 bits
- Configurable shift size/oversampling on RX
- Optional RX frame size auto shut off
- Programmable HW delay 1 (wire delay, controlling when the clock signal is first driven low) and delay 2 (tst delay, controlling when the clock signal is first driven high) on TX operation
- Optional programmable TX termination
- Individual TX channel start trigger (tx_channel_go) or simultaneous TX start trigger for all channels (tx_global_go)
- Flexible HW assisted clock output generation to allow free running, stop high and stop low (after last RX data), or stop high (after last TX data) operation with optional software clock override feature
- Optional SW direct snoop of data input
- RX Start Bit of '1' or '0'