SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
Each SOC can be configured to convert any of the ADC channels. This behavior is selected for SOCx by the ADCSOCxCTL.CHSEL register. This is summarized in Table 15-4.
Input Mode | CHSEL | Input | |
---|---|---|---|
Single-Ended | 0 | ADCIN0 | |
1 | ADCIN1 | ||
2 | ADCIN2 | ||
3 | ADCIN3 | ||
4 | ADCIN4 | ||
5 | ADCIN5 | ||
6 | ADCIN6 | ||
7 | ADCIN7 | ||
8 | ADCIN8 | ||
9 | ADCIN9 | ||
10 | ADCIN10 | ||
11 | ADCIN11 | ||
12 | ADCIN12 | ||
13 | ADCIN13 | ||
14 | ADCIN14 | ||
15 | ADCIN15 |