SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
The CPU provides a clock (SYSCLK) to the private (M0 and M1), local shared (LS4 to LS7) and global shared (GS0) RAMs, boot ROM and other peripherals. This clock is identical to PLLSYSCLK, but is gated when the CPU enters HALT or STANDBY mode.
Each peripheral clock has its own independent clock gating which is controlled by the PCLKCRx registers.
Application needs to wait for 5 SYSCLK cycles after enabling clock to the peripherals when using PCLKCRx.