SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

3.3 Configuring a CLB Tile

To open the SysConfig tool, double-click on the “.syscfg” file you want to edit in the CCS Project Explorer window. A screen like that is shown in Figure 3-5.

GUID-9B059995-5066-4826-8008-EAEC61809206-low.png Figure 3-5 CLB Tool SysConfig Screen

If this screen does not open, be sure you have correctly completed the steps before this.

The configuration of CLB tiles are contained in the .syscfg file. You can change the name of the tile if desired. For the highlighted tile a list of sub-modules is shown in the pane to the right. The parameters of each sub-system can be inspected and edited by selecting the sub-module.

The “BOUNDARY” item is a special case. This group allows the user to select the tile inputs for simulation only. When the tool configuration is generated the CLB inputs always come from the CLB module within SysConfig, but for the purposes of simulation the user can specify a square wave signal source, together with a period and duty (both in clock cycles), synchronization, and input pipeline conditions as shown in Figure 3-6. Custom waveform generation for simulation purposes is also supported. For more information on the simulator, see Section 3.5. These options are only for simulation and do not affect the actual CLB configuration or its implementation on the device.

GUID-69A31E79-C0E3-461B-88A8-29AB2873825B-low.png Figure 3-6 Boundary Input Options

The user configures and connects sub-modules in each tile using the check-boxes and drop-down options in the tool. All the sub-modules besides "BOUNDARY" also have a "User Description". This description is a multi-line text box where users can enter comments to help contextualize each part of the CLB.

GUID-931FCC0C-8224-43F5-A2D5-324068DAF7B2-low.png Figure 3-7 User Description Text Box

Context sensitive help appears when the mouse cursor is hovered over each item in the configuration tool. Figure 3-8 shows an example for the "Match Reference 1" field in the "Counter 0" sub-module.

GUID-8E32C4AF-199C-4E4C-A11E-C6CFC88930A9-low.png Figure 3-8 Counter Options

Logical equations for the LUTs and FSMs are configured by text entry using C format. Table 3-2 shows the symbols that are allowed in a Boolean equation.

Table 3-1 Supported Logical Operations
Logical Operation Symbol
AND &
OR |
XOR ^
NOT !

The use of parentheses is supported: for example, one could write: i1 | !(i2 & i3). The tool performs syntax checking on the equations as they are entered. Invalid equations are indicated by an error message below the entry line.

Some unlikely logical combinations generate a warning to the user. Figure 3-9 shows an example in which the user has attempted to use the i2 input in "LUT 0" in a Boolean equation. However, i2 is configured to be a constant which is unlikely to be what the user intended. The warning appears both below the equation and below the input selection.

GUID-9B6DD27C-5996-40D9-9683-10FA1FDF1772-low.png Figure 3-9 Equation Warning

For some fields, the tool performs range checking on numerical entries to ensure they lie within the allowable range. For example, an attempt to load a counter sub-module with a value greater than 232 will produce a warning because the counter is only 32 bits wide.

The tool automatically generates a number of files as the user enters configuration data. To view the generated files, click on the "< >” symbol in the upper right corner of the tool and select the filename to open it.

GUID-1E169C31-AE6C-41F7-9201-1277A9665A99-low.png Figure 3-10 CLB Tool Generated Files

CLB register settings are contained in the header file “clb_config.h”, which can be opened by the user by clicking the filename. An example is shown in Figure 3-11. It is important to understand that this file is updated by the tool each time the user changes any CLB Tile Design settings. Therefore, manual changes to the contents of the generated files will be over-written by the tool. If the file is kept open while changing CLB settings, the the affected register data changing in the file can be viewed when the 'Unified Diff' option is selected.

GUID-26BB5B30-DF87-4C89-B1E9-F5FD28B1C196-low.png Figure 3-11 “clb.h” Header File Example

The file “clb.dot” allows the user to inspect a visual representation of the inter-connection of sub-modules. HTML and SVG versions of this block diagram are generated in the post-build steps that can be opened and viewed inside CCS.

GUID-D6586B1C-D223-4FCE-B466-83F64C37DB7B-low.svg Figure 3-12 CLB Block Diagram

Fields for the HLC sub-module include those for configuring the events and initial values. Each of the four events can trigger execution of a short program consisting of up to eight instructions. For more information on the HLC, see the device-specific TRM.

HLC instructions can be entered in the "HLC Program" drop-down in "Other Dependencies". One blank line is always shown until all eight instructions have been used. In Figure 3-13, the user has selected one HLC trigger events and typed in a short program consisting of three instructions.

GUID-6608638A-69CF-4B8C-8576-0DF61A1D2C57-low.png Figure 3-13 HLC Configuration Example