SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

4.2.11 Example 17 – One-Shot PWM Generation

This example demonstrates how a CLB tile can be configured to act as a one-shot PWM generator. The example makes use of combinatorial logic (LUTs), state machines (FSMs), counters, and the HLC to demonstrate the one-shot PWM output generation capabilities on receipt of an external/software trigger.

GUID-A90DD559-F896-486B-9D79-D2CC981BB1E6-low.gif Figure 4-13 Example 17: One-Shot PWM Output

The CLB tile is configured to simulate a one-shot timer on receipt of a trigger the timer starts counting from zero, reaches the MATCH value and then stops counting till the next trigger is received. The output is driven HIGH while counter is counting and is driven LOW when counter reaches the MAX and stops counting. The above logic is implemented using LUT, FSM and counter. Another counter is used to make sure that the following system responds only to a rising edge event instead of input level. The example also supports variable pulse width using HLC submodule and CLB interrupt mechanism. The HLC is used to generate an interrupt after every 3rd trigger event (which is tracked by another counter) and the pulse width is updated by the application. The range of the output pulse width configured in the example is 0.2 µs - 0.8 µs with a step increase of 50 ns in every interrupt ISR. The PWM register is configured to use active and shadow registers, which is also done using the HLC block.

The overall CLB configuration can be visualized as shown in Figure 4-14.

GUID-474D1B1A-0D76-4D36-A8F4-6DE2D6CEEC0C-low.gif Figure 4-14 Example 17: Overall CLB configuration

The example supports two modes of configuration: software based trigger and external signal based trigger. The desired mode can be chosen by setting the EXAMPLE_MODE define as 0/1. In case of software based trigger, you can manually update the SOFT_TRIGGER from 0 to 1 in CCS expression window and observe the one-shot pulse output on oscilloscope. Note to make sure that the variable was set to ‘0’ before setting it to ‘1’, because the CLB system responds only to a rising edge. While in the case of external signal based trigger, the EPWM module is configured to generate a trigger signal of 1 MHz with a very short ON time (10% duty). This EPWM generated signal on GPIO0 is routed as the trigger input for CLB internally, thus no external connections are required.

To run the example, follow this procedure:

  1. In CCS v9.0 or higher, click “Project -> Import CCS Projects…”
  2. Navigate to the CLB tool example directory. The path is:
    1. [C2000Ware]\driverlib\f28004x\examples\clb\ccs, or In the description that follows, it is assumed the C2000Ware directory above is in use.
  3. Select the project “clb_ex17_one_shot_pwm”, and click “Finish”.
  4. In the CCS Project Explorer window, expand the project “clb_ex17_one_shot_pwm” and open the file “clb_ex17_one_shot_pwm.syscfg”.
  5. Inspect the configuration of the tile and observe the logical expressions in LUT_0 and FSM_0, COUNTER_0, COUNTER_1, COUNTER_2,HLC and the output LUT.
  6. Configure EXAMPLE_MODE as 0/1 to operate in software/external trigger mode.
  7. From the CCS menu, select “Project -> Build Project”.
  8. [Optional] – for instructions on how to run a simulation of the CLB, see Section 3.5.3.
  9. Load the example on F28004x control card.
  10. If software trigger mode is chosen:
    1. Add SOFT_TRIGGER variable to CCS expression window.
    2. Connect GPIO2 to oscilloscope and make sure the oscilloscope is in “One-shot” mode instead of “FREE_RUN”.
    3. Run the example and set SOFT_TRIGGER = 1 in window, you should be able to observe the single pulse on oscilloscope.
    4. Set SOFT_TRIGGER = 0 first and then SOFT_TRIGGER = 1 to generate the next pulse.
    5. Repeat the above step every time to provide rising edge trigger.
    6. After every three triggers, the pulse would be increased by 50 ns.
  11. If external trigger mode is chosen:
    1. Connect GPIO0 (trigger signal) and GPIO2 (output) to the oscilloscope and configure the oscilloscope in FREE_RUN mode.
    2. You should observe a linear variation in output pulse width after every 3rd rising edge of trigger signal.