This example configures a CLB tile as an auxiliary PWM generator. The example uses combinatorial logic (LUTs), state machines (FSMs), counters, and the high level controller (HLC) to demonstrate the PWM output generation capabilities using CLB.

The PWM generator operates at the CLBCLK frequency. The FSM is used to set/clear the PWM. The PWM is set on a CMP match event, which is tied to match2 of the COUNTER_0. The PWM is cleared on a Zero match event (Z). This event is tied to the COUNTER_0 match1 output.

The PWM register is configured to use active and shadow registers, which is done using the HLC block. The HLC is used to generate an interrupt on the period match event, match1. When an interrupt occurs, a new counter match value is loaded into the HLC register (R0). The new counter match value is then moved into the match2 register of COUNTER_0. This updates the CMP match value, which in turn updates the value of the positive duty cycle. In this example, the user alternates between two values for the positive duty cycle. Figure 4-1 shows in principle what the PWM generator does. Notice how the duty cycle in the next period is changed.

The CLB tile takes a PWM enable signal as input and generates an interrupt to the CPU. The CLB tile is configured to use a counter to count up until the desired period and compare event values are met. When the counter reaches the compare event match value, at output ‘match2’, the output is driven high and remains high until the counter value for the period match, at output ‘match1’, is met or a counter reset is triggered. When the period event or reset occurs, the counter is reset to 0 and the output is driven low and the counter begins counting up. This output logic is configured using the logical equation entered in the FSM. In this example, the period is 300 CLBCLK cycles (3 µs). The compare event occurs at either 100 CLBCLK cycles (1 µs) or 150 CLBCLK cycles (1.5 µs).

The PWM signal can be viewed by feeding the output of the FSM into OUTLUT_4. In order to view the output on a scope, it has to be transmitted via the Output X-BAR to the GPIO Mux.

To run the example, follow this procedure:

1. In CCS v9.0 or higher, click “Project → Import CCS Projects…”.
2. Navigate to the CLB tool example directory. The path is:
   1. [C2000Ware]\driverlib\f2837xd\examples\cpu1\clb\ccs, or
   2. [C2000Ware]\driverlib\f28004x\examples\clb\ccs, or
   3. [C2000Ware]\driverlib\f2838x\examples\c28x\clb\ccs

   In the description that follows, it is assumed the C2000Ware directory above is in use.

3. Select the project “clb_ex3_auxiliary_pwm”, and click “Finish”.
4. In the CCS Project Explorer window, expand the project and open the file “clb_ex3_aux_pwm.syscfg”.
5. Inspect the configuration of the tile and observe the logical expressions in LUT4_0, COUNTER_0, FSM_0, and the configuration of the HLC and the output LUT.
6. From the CCS menu, select “Project → Build Project”.
7. View the CLB Tile block diagram by opening the "Debug/syscfg/clb.html" file
8. [Optional] – for instructions on how to run a simulation of the CLB, see Section 3.5.3.
9. To view the PWM and interrupt signals, set up an oscilloscope and monitor the following pins while the program is running. The table below shows the pin to monitor for each respective board.

   Signal	F28379D LaunchPad	F280049 controlCARD	F28388D controlCARD
   Interrupt	GPIO0 on pins J4/40	pin 49 (GPIO0)	pin 49 (GPIO0)
   Auxiliary PWM	OutputXBAR1 signal on pins J4/34	pin 53 (OutputXBAR1)	pin 53 (OutputXBAR1)

10. Open a CCS Expressions window and add the program variable dutyValue. While the program is running, you will notice the CMPA value alternates between 100 and 150 CLBCLK cycles every time the CLB interrupt is serviced. The signals should be as shown in the timing diagram above. Notice that the PWM period remains the same but the positive duty cycle alternates between 50% and 66%. The dutyValue variable can be modified within the interrupt service routine.