SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

4.2.2 Example 2 – GPIO Input Filter

This example demonstrates use of finite state machines (FSMs) and counters to implement a simple ‘glitch’ filter which might, for example, be applied to an incoming GPIO signal to remove unwanted short duration pulses.

Figure 4-7 shows in principle what the glitch filter does. An incoming digital signal is sampled at the CLB clock rate and a counter counts the number of consecutive samples where the input is either high or low. If this number is equal to or greater than a specified sample window, the filter output takes on the same value as the input; otherwise the filter output does not change. Figure 4-7 shows in principle what the filter does.

GUID-BD7925B8-1358-4E6C-AA7F-C4944BC544F4-low.gif Figure 4-7 Example 2: GPIO Glitch Example

The CLB configuration uses one LUT4 to invert the incoming signal, and two counters to count the number of pulses: one counter for the high pulses, the other for low pulses. When either counter reaches the sample window length a pulse appears at its ‘match1’ output. In this example the filter sample window length is set to eight. An FSM latches the pulse and implements a simple logic equation to determine the required level at its ‘S0’ state output. One output LUT is used to convey the FWM output to the peripheral signal multiplexer for connection to GPIO0. The CLB configuration is shown in Figure 4-8.

GUID-3D57DDAF-0D4D-46B8-B92B-BD0FE0515AF7-low.gif Figure 4-8 Example 2: CLB Configuration

The example code configures the ePWM1 module to generate the test stimulus.

To run the example, follow this procedure:

  1. In CCS v9.0 or higher, click “Project → Import CCS Projects…”.
  2. Navigate to the CLB tool example directory. The path is:
    1. [C2000Ware]\driverlib\f2837xd\examples\cpu1\clb\ccs, or
    2. [C2000Ware]\driverlib\f28004x\examples\clb\ccs, or
    3. [C2000Ware]\driverlib\f2838x\examples\c28x\clb\ccs

    In the description that follows, it is assumed the C2000Ware directory above is in use.

  3. Select the project “glitch_filter” and click “Finish”.
  4. In the CCS Project Explorer window, expand the project “glitch_filter” and open the file “tile.syscfg”.
  5. Inspect the configuration of the tile and observe the settings of the sub-modules LUT4_0, COUNTER_0, COUNTER_1, and FSM_0. Verify that the configuration matches that in the example description above.
  6. From the CCS menu, select “Project → Build Project”.
  7. [Optional] – for instructions on how to run a simulation of the CLB, see Section 3.5.3.

If running the program on an F28379D LaunchPad board, PWM signals 1A and 1B can be monitored on pins J4/40 and J4/39, respectively. Set up an oscilloscope to monitor the signals at these pins while the program is running. If running the program on an experimenter’s kit fitted with a F280049 or F28388D controlCARD, the signals can be found on pins 49 and 51, respectively.

Open a CCS Expressions window and add the program variable “cglitch”. Run the program while observing PWM signals 1A and 1B. Pause the program and change the value of “cglitch”, then re-start the program (this process is easier if the expressions window is set to run in “continuous refresh”). For values of 7 or less the glitch should be removed by the filter because its’ width is less than the sample window. When “cglitch” is higher than 7 the glitch should appear on both outputs. Notice also that edges on PWM1A have a small delay compared with those on PWM1B. This is a consequence of the filter method used.

Figure 4-9 shows the expected waveforms at the output pins for glitch widths below and above the sample window setting of 8.

GUID-EEBFFD9A-4F8F-4024-B38B-7970D94DF56E-low.gif Figure 4-9 Example 2: GPIO Glitch Width