SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Ring Accelerator implementation
Supports up to 32 independent memory mapped ring structure
Supports various modes for each ring based on usage and compatibility
Provides single word deep shared incoming Transfer Response FIFO
Optionally supports dynamic clock gating
Provides bit wide source VBUSM read/write target interface for accesses from DMA controller entities
Provides 2 word deep command FIFO
Provides 2 word deep write data FIFO
Provides 2 word deep read data FIFO
Provides 2 word deep write status FIFO
Provides bit wide destination VBUSM read/write initiator interface for accesses to ring structures in memory
Supports up to 16 outstanding writes
Supports up to 16 outstanding reads
Provides 2 word deep command FIFO
Provides 2 word deep write data FIFO
Provides 2 word deep read data FIFO
Provides 2 word deep write status FIFO
Source interface provides an array of 32x512-byte long address windows (four for each ring) which are packed into a single contiguous address range.
Read and write addresses which target a specific window are mangled to redirect the read or write transaction to an effective address calculated from the base address for the ring plus current ring offset.
Each read or write access presented on VBUSM target interface is modified and bridged onto the VBUSM initiator interface.