SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
This section defines how the DIG_CORE Shadow MMRs maintain coherences with the DIG_ON Live MMR domain. All vbusp transactions terminate in the DIG_CORE block. All vbusp write transaction which require DIG_ON updates is completed by the Shadow to Live HW sequencer.
This HW sequencer has 2 modes of operation.
In Delayed Write Mode
For example, HOST PROCESSOR updates OFF_ON_S_CNT_LSW and OFF_ON_S_CNT_MSW.
After the HOST PROCESSOR completes the OFF_ON_S_CNT_MSW, the HW sequencer will start the process of updating the DIG_ON domain at the first available 32khz_clk is low cycle.
ALL MMR write transaction require full 4 Bytes writes in order to reduce the logic size of the DIG_ON domain.
RULE: Require 4 Bytes writes (less logic and iso)
Due to this fact, the HOST PROCESSOR must first unlock write access by performing the unlock sequence, by simply writing Kick0 and Kick1 with the correct pattern and sequence. After this is done, the RTC is in an unlock date. The HOST PROCESSOR will need to relocking by writing any pattern to Kick1