SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The Peripheral I/F module has two source clock options, PRU_ICSS_UART_CLK (default) and PRU_ICSS_ICLK. There are two independent clock dividers (div16) for the 1x and oversampling (OS) clocks, and each clock divider is configurable by two cascading dividers:
The 1x clock is output on the PERIF<m>_CLK signal. In TX mode, the output data is read from the TX FIFO at this 1x clock rate. The default value of this clock is high and the start and stop conditions for this clock are described in Section 4.4.2.2.3.6.3.2Clock Output Start Conditions and Section 4.4.2.2.3.6.3.3Stop Conditions.
In RX mode, the input data is sampled at the OS clock rate. Note: The OS clock rate divided by the 1x clock rate must equal [2-0] PRU0_ED_RX_SAMPLE_SIZE.
Example clock rates and divisor values relative to the 192-MHz PRU_ICSS_UART_CLK source are shown in Table 7-55.
| TX_DIV_FACTOR | 1x Clock | RX_DIV_FACTOR | RX_DIV_FACTOR_FRAC | OS Clock | Oversample Factor |
|---|---|---|---|---|---|
| 12 | 16 MHz | 1 | 1.5 | 128 MHz | 8x |
| 16 | 12 MHz | 2 | 1 | 96 MHz | 8x |
| 24 | 8 MHz | 3 | 1 | 64 MHz | 8x |
| 32 | 6 MHz | 4 | 1 | 48 MHz | 8x |
| 48 | 4 MHz | 6 | 1 | 32 MHz | 8x |
| 96 | 2 MHz | 12 | 1 | 16 MHz | 8x |
| 192 | 1 MHz | 24 | 1 | 8 MHz | 8x |