SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Because of the pipelined behavior of the system, successive accesses to different chip-selects can occur back-to-back with no idle cycles between accesses. Depending on the control signals (nCS, nADV/ALE, nBE0/CLE, nOE/RE, nWE) assertion and deassertion timing parameters and on the device timing parameters, the assertion times of some control signals may overlap between the successive accesses to a different chip-select. Similarly, some control signals (WE, OE/RE) may not respect required transition times.
To work around overlapping and to observe the required control-signal transitions, a minimum of CYCLE2CYCLEDELAY inactive cycles is inserted between the access being initiated to this chip-select and the previous access ending for a different chip-select. This applies to any type of access (read or write).
If the GPMC_CONFIG6_i[6] CYCLE2CYCLEDIFFCSEN bit is enabled, the chip-select access is delayed until CYCLE2CYCLEDELAY cycles have expired since the end of a previous access to a different chip-select. CYCLE2CYCLEDELAY count starts at CSRDOFFTIME/CSWROFFTIME completion. All control signals are kept inactive during the idle GPMC_FCLK cycles.
CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDIFFCSEN must be set in the GPMC_CONFIG6_i registers to get idle cycles inserted between accesses on this chip-select and after accesses to a different chip-select, respectively.
The CYCLE2CYCLEDELAY delay runs in parallel with the BUSTURNAROUND delay. The BUSTURNAROUND is a timing parameter defined for the ending chip-select access, whereas CYCLE2CYCLEDELAY is a timing parameter defined for the starting chip-select access. The effective minimum delay between successive accesses is based on the larger delay timing parameter and on access type combination, because bus turnaround does not apply to all access types. For more information about bus turnaround, see Section 4.3.4.7.3.1.6.1, Bus Turnaround (BUSTURNAROUND).
Table 12-192 describes the configuration required for idle cycle insertion.
| 1st Access Type | BUSTURN AROUND Timing Parameter | Second Access Type | Chip- Select | Add/Data Multiplexed | CYCLE2 CYCLE SAMECSEN Parameter | CYCLE2 CYCLE DIFFCSEN Parameter | Idle Cycle Insertion Between the Two Accesses |
|---|---|---|---|---|---|---|---|
| R/W | = 0 | R/W | Any | Any | 0 | x | No idle cycles are inserted if the two accesses are well pipelined. |
| R | > 0 | R | Same | Nonmuxed | x | 0 | No idle cycles are inserted if the two accesses are well pipelined. |
| R | > 0 | R | Different | Nonmuxed | 0 | 0 | BUSTURNAROUND cycles are inserted. |
| R | > 0 | R/W | Any | Muxed | 0 | 0 | BUSTURNAROUND cycles are inserted. |
| R | > 0 | W | Any | Any | 0 | 0 | BUSTURNAROUND cycles are inserted. |
| W | > 0 | R/W | Any | Any | 0 | 0 | No idle cycles are inserted if the two accesses are well pipelined. |
| R/W | = 0 | R/W | Same | Any | 1 | x | CYCLE2CYCLEDELAY cycles are inserted. |
| R/W | = 0 | R/W | Different | Any | x | 1 | CYCLE2CYCLEDELAY cycles are inserted. |
| R/W | > 0 | R/W | Same | Any | 1 | x | CYCLE2CYCLEDELAY cycles are inserted. If BTA idle cycles already apply on these two back-to-back accesses, the effective delay is max (BUSTURNAROUND, CYCLE2CYCLEDELAY). |
| R/W | > 0 | R/W | Different | Any | x | 1 | CYCLE2CYCLEDELAY cycles are inserted. If BTA idle cycles already apply on these two back-to-back accesses, the effective delay is maximum (BUSTURNAROUND, CYCLE2CYCLEDELAY). |