SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Bits | Field | Reset | Description |
---|---|---|---|
31 | enable | 0x0 |
When set, the channel is enabled. When cleared, the TX channel is disabled. When disabled, it discards all held data. It clears DMA event counts and ignores all future DMA events from the peripheral. It maintains data exchange with the UDMA-P so that credit handshake is not disrupted. A 'hard teardown' can be performed by directly clearing this bit. Note that this bit cannot be changed from 0 to 1 if the global enable bit in the peer enable register is 0. |
30 | tdown | 0x0 |
When set, the channel will commence a TX channel teardown procedure. To perform a TX teardown, the teardown bit should be set in the UDMA-P and it will automatically propagate to this register bit with the normal flow of peripheral data. Once the channel is fully stopped and ready to be reused (including returning all credits), the enable bit is cleared. |
29 | pause | 0x0 | When set, the channel is in a paused state. It will stop on the next FIFO boundary. It continues to accept and count DMA events from the peripherals, but will not act on them. The pause bit can be cleared and data will resume. |
28 | flush | 0x0 | When set, causes all TX channel data to be discarded instead of being written to the peripheral. It essentially allows the TX engine to 'free run' without DMA requests from the peripheral (it will also override 'pause'). This bit should be set only when a channel fails to complete its teardown procedure normally, because a peripheral is no longer functioning or because data flow was halted on a boundary that is not compatible with the static TR configuration. |
27:3 | - | 0x0 | Reserved. |
2 | error | 0x0 | When set, the channel has encountered a PSIL protocol violation. The error bit can only be set by hardware, and can only be cleared by software. Once this bit is set, the channel should be fully reset and re-initialized via the PSIL pairing registers. |
1 | idle | 0x0 | This is a read-only bit that signifies that the disabled channel is also idle. This bit is read only and can only become set if the enable bit in the RT enable register is cleared. |
0 | free | 0x0 | When cleared, the channel honors the emudbg suspend signal. When set, the channel will free run, regardless of the value of emudbg suspend. |