SPRUIW4 October 2021 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Color | Description |
---|---|
Options common for both devices but BOOTDEFx values may differ | |
Options applicable only for F28002x | |
Options applicable only for F28003x |
Bootloader | Option | BOOTDEFx | F28002x | F28003x |
---|---|---|---|---|
Parallel | 0 | 0x00 | D0-D7=0 to 7; DSP=16; Host=29 |
D0-D7=0 to 7; DSP=16; Host=29 |
1 | 0x20 | D0-D7=0 to 7; DSP=16; Host=11 |
D0-D7=0 to 7; DSP=16; Host=11 |
|
SCIA | 0 | 0x01 | TX=29; RX=28 |
TX=29; RX=28 |
1 | 0x21 | TX=16; RX=17 |
TX=16; RX=17 |
|
2 | 0x41 | TX=8; RX=9 |
TX=8; RX=9 |
|
3 | 0x61 | TX=2; RX=3 |
TX=2; RX=3 |
|
4 | 0x81 | TX=16; RX=3 |
TX=16; RX=3 |
|
CAN | 0 | 0x02 | TX=4; RX=5 |
TX=4; RX=5 |
1 | 0x22 | TX=32; RX=33 |
TX=32; RX=33 |
|
2 | 0x42 | TX=2; RX=3 |
TX=2; RX=3 |
|
3 | 0x62 | n/a | TX=13; RX=12 |
|
MCAN | 0 | 0x08 | n/a | TX=4; RX=5 |
1 | 0x28 | n/a | TX=1; RX=0 |
|
2 | 0x48 | n/a | TX=13; RX=12 |
|
SPI | 0 | 0x06 | SIMO=2 SOMI=1; CLK=3; STE=5 |
SIMO=2 SOMI=1; CLK=3; STE=5 |
1 | 0x26 | SIMO=16 SOMI=1; CLK=3; STE=0 |
SIMO=16 SOMI=1; CLK=3; STE=0 |
|
2 | 0x46 | SIMO=8 SOMI=10; CLK=9 STE=11 |
SIMO=8 SOMI=10; CLK=9; STE=11 |
|
3 | 0x66 | SIMO=8 SOMI=17; CLK=9; STE=11 |
SIMO=8 SOMI=17; CLK=9; STE=11 |
|
I2C | 0 | 0x07 | SDA=32 SCL=33 |
SDA=32; SCL=33 |
1 | 0x27 | SDA=0; SCL=1 |
SDA=0; SCL=1 |
|
2 | 0x47 | SDA=10; SCL=8 |
SDA=10; SCL=8 |
Boot Mode | Option | BOOTDEFx | F28002x | F28003x |
---|---|---|---|---|
Flash | 0 | 0x03 | Entry=0x00080000' Bank/Sector=0/0 |
Entry=0x00080000; Bank/Sector=0/0 |
1 | 0x23 | Entry=0x00084000; Bank/Sector=0/4 |
Entry=0x00088000; Bank/Sector=0/8 |
|
2 | 0x43 | Entry=0x00088000; Bank/Sector=0/8 |
Entry=0x0008FFF0; Bank/Sector=0/15 |
|
3 | 0x63 | Entry=0x0008EFF0; Bank/Sector=0/14 |
Entry=0x00090000; Bank/Sector=1/0 |
|
4 | 0x83 | - | Entry=0x00097FF0; Bank/Sector=1/7 |
|
5 | 0xA3 | - | Entry=0x0009FFF0; Bank/Sector=1/15 |
|
6 | 0xC3 | - | Entry=0x000A0000; Bank/Sector=2/0 |
|
7 | 0xE3 | - | Entry=0x000AFFF0; Bank/Sector=2/15 |
|
LFU Flash | 0 | 0x0B | - | Entry=0x00080000; Bank=0 Entry=0x00090000; Bank=1 Entry=0x000A0000 Bank=2 |
1 | 0x2B | - | Entry=0x00088000; Bank=0 Entry=0x00098000; Bank=1 Entry=0x000A8000 Bank=2 |
|
2 | 0x4B | - | Entry=0x0008FFF0; Bank=0 Entry=0x0009FFF0; Bank=1 Entry=0x000AFFF0 Bank=2 |
|
3 | 0x6B | - | Entry=0x00088000; Bank=0 Entry=0x00090000; Bank=1 Entry=0x000A0000 Bank=2 |
|
4 | 0x8B | - | Entry=0x0008EFF0; Bank=0 Entry=0x00097FF0; Bank=1 Entry=0x000A7FF0 Bank=2 |
|
Secure LFU Flash | 0 | 0x0C | - | Entry=0x00080000; Bank=0 Entry=0x00090000; Bank=1 Entry=0x000A0000 Bank=2 |
1 | 0x2C | - | Entry=0x00088000; Bank=0 Entry=0x00098000; Bank=1 Entry=0x000A8000 Bank=2 |
|
2 | 0x4C | - | Entry=0x0008FFF0; Bank=0 Entry=0x0009FFF0; Bank=1 Entry=0x000AFFF0 Bank=2 |
|
3 | 0x6C | - | Entry=0x00088000; Bank=0 Entry=0x00090000; Bank=1 Entry=0x000A0000 Bank=2 |
|
4 | 0x8C | - | Entry=0x0008EFF0; Bank=0 Entry=0x00097FF0; Bank=1 Entry=0x000A7FF0 Bank=2 |
|
Wait | 0 | 0x04 | Watchdog enabled | Watchdog enabled |
1 | 0x24 | Watchdog disabled | Watchdog disabled | |
RAM | 0 | 0x05 | Entry=0x00000000 | Entry=0x00000000 |