SPRUIW7A October 2020 – February 2022
Table 3-6 shows the J7200 SOM configuration switches (SW1-SW4) to set the various functions SOM.
Switch Name | Default Condition | Signal | Operation |
---|---|---|---|
SW1 | OFF | CANIO_RET_WAKE | Use as generic input (Push Button). Can be used as wake when system in IO retention mode |
SW2.1 | NA | NA | Not used |
SW2.2 | ON | LEOA_WDOG_DISABLE | Enable/Disable selection for PMIC Watchdog Timer: ‘0’ (OFF) = PMIC watchdog timer is enabled ‘1’ (ON) = PMIC watchdog timer is disabled (Default) |
SW3.1 | OFF | SOC_SAFETY_ERRz | Option to combine SOC_SAFETY_ERRz with MCU_SAFETY_ERR and PMIC. ‘0’ (OFF) = SOC_SAFETY_ERRz (Main) is isolated from PMIC. (Default) ‘1’ (ON) = SOC_SAFETY_ERRz (Main) is connected to PMIC. |
SW3.2 | OFF | SOC_PWR_EN | Manual method of enabling PMIC ‘0’ (OFF) = PMIC enabled by EVM system (Default) ‘1’ (ON) = PMIC enabled manually (test mode only) |
SW4.1 | OFF | VDDR_IO_DV_SRC_FB | Selects the I/O voltage level for LPDDR4: ‘0’ (OFF) = Selects 1.1 V I/O for LPDDR4 (Default) ‘1’ (ON) = Selects 0.6 V I/O for LPDDR4X (Not supported) |
SW4.2 | OFF | SEL_SOC_I2Cn | MUX to select I2C Interface for PMICs: ‘0’ (OFF) = PMIC I2C to SoC WKUP I2C (Default) ‘1’ (ON) = PMIC I2C to Ext header I2C (test mode only) |