SPRUIW7A October   2020  – February 2022

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 Electrostatic Discharge (ESD) Compliance
  3. 2J7200 EVM Overview
    1. 2.1 J7200 EVM Board Identification
    2. 2.2 J7200 SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Component Identification
    4. 2.4 Quad Ethernet Components Identification
  4. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
  5. 4J7200 EVM Hardware Architecture
    1. 4.1  J7200 EVM Hardware Top Level Diagram
    2. 4.2  J7200 EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
      4. 4.5.4 J7200 SoC SLEEP Logic Operation
      5. 4.5.5 J7200 SoC MCU Only Operation
      6. 4.5.6 J7200 SoC GPIO Retention Operation
      7. 4.5.7 J7200 SoC DDR Retention Operation
      8. 4.5.8 Power Monitoring
      9. 4.5.9 Power Test Points
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 MMC Interface
        1. 4.8.3.1 MMC0 - eMMC Interface
        2. 4.8.3.2 MMC1 – Micro SD Interface
      4. 4.8.4 Board ID EEPROM Interface
      5. 4.8.5 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X2 Lane PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
        1. 4.12.2.1 To PCIe Card Wi-Fi/BT
        2. 4.12.2.2 To Expansion Connector
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 Audio Interface
      1. 4.13.1 Line IN Port
      2. 4.13.2 MIC Input Port
      3. 4.13.3 Line Out Port
      4. 4.13.4 Head Phone Port
      5. 4.13.5 Port Mapping
    14. 4.14 CAN Interface
      1. 4.14.1 MCU CAN0
      2. 4.14.2 MCU CAN1
      3. 4.14.3 MAIN CAN3 (supports WAKE function)
      4. 4.14.4 MAIN CAN0
    15. 4.15 FPD Interface (Audio Deserializer)
    16. 4.16 I3C Interface
      1. 4.16.1 Gyroscope
      2. 4.16.2 I3C Header
    17. 4.17 ADC Interface
    18. 4.18 RTC Interface
    19. 4.19 Apple Authentication Header
      1. 4.19.1 Module Interface
    20. 4.20 JTAG Emulation
    21. 4.21 EVM Expansion Connectors
    22. 4.22 ENET Expansion Connector
      1. 4.22.1 Power Requirements
      2. 4.22.2 Clock
        1. 4.22.2.1 Main Clock
        2. 4.22.2.2 Optional Clock
      3. 4.22.3 Reset Signals
      4. 4.22.4 Ethernet Interface
        1. 4.22.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.22.5 Board ID EEPROM Interface
  6. 5Functional Safety
  7. 6Revision History

4.4 GPIO Mapping

The general purpose IOs (GPIOs) of the SoC have two major groups as WKUP/MCU and MAIN. Table 4-3 describes the detailed GPIO mapping of SoC with EVM peripherals.

Table 4-3 J7200 SoC - GPIO Mapping Table
J7200 SoC - GPIO Mapping Table
Package Signal Name GPIO Number Net name Input/Output Default State Remarks
WKUP Domain
WKUP_GPIO0_0 WKUP_GPIO0_0 MCU_MCAN0_EN Output BOOTMODE Active High MCU CAN0 Enable
WKUP_GPIO0_1 WKUP_GPIO0_1 BOOT_EEPROM_WP Output BOOTMODE Active High Boot EEPROM Write protect
WKUP_GPIO0_2 WKUP_GPIO0_2 MCU_CAN1_STB Output BOOTMODE Active High MCU CAN1 Standby
WKUP_GPIO0_3 WKUP_GPIO0_3 GPIO_MCU_RGMII1_RST# Output PU Active low MCU_RGMII1_Reset
WKUP_GPIO0_6 WKUP_GPIO0_6 OSPI/HYPER_MUX_SEL Output DIP_SEL NA Flash Memory Selection ('0' - OSPI0, '1' - Hyperflash + HyperRam)
WKUP_GPIO0_7 WKUP_GPIO0_7 SYS_IRQz Input PU Active low Push-button Interrupt, User Defined/Wake S2R ('0>1' - interrupt pending, '1' - normal operation)
MCU_OSPI0_LBCLKO WKUP_GPIO0_17 MCU_OSPI0_ECC_FAIL Output NA Active High OSPI_ECC_FAIL (Mux option w/ MCU_HYPERBUS0_INT#),
MCU_SPI0_CLK WKUP_GPIO0_56 PROFI_UART_SEL Output PD Active High Signal Mux Control ('0' - Profibus, '1' - BP/MC UART)
MCU_SPI0_D0 WKUP_GPIO0_57 SYS_MCU_PWRDN Output PD Active low System Power Down ('0' - normal operation, '1' - system power down)
MCU_SPI0_D1 WKUP_GPIO0_58 MCU_CAN0_STBz Output BOOTMODE Active low MCU CAN0 Standby
MCU_SPI0_CS0 WKUP_GPIO0_59 MCU_RGMII1_INT# Input PU Active Low MCU Ethernet Interrupt ('0' - interrupt pending, '1' - no interrupt)
WKUP_GPIO0_77 WKUP_GPIO0_77 WKUP_GPIO0_77 Output BOOTMODE NA Open (GPIO not used)
WKUP_GPIO0_78 WKUP_GPIO0_78 H_MAIN_GPIO_A Output BOOTMODE NA Open (GPIO not used)
WKUP_GPIO0_80 WKUP_GPIO0_80 LSM6DSOX_INT Output BOOTMODE NA Open (GPIO not used)
WKUP_GPIO0_84 WKUP_GPIO0_84 H_MCU_INT# Input PU Active low Interrupt from PMIC
Main Domain
EXTINTn GPIO0_0 SOC_EXTINTN Input PU Active low Push-button Interrupt, User Defined
MCAN1_RX GPIO0_12 CANIO_RET_WAKE Input PU NA Push-button wake signal,
MCAN9_RX GPIO0_28 GPIO_RGMII2_RST I/O NA NA Routed to INFO/GESI expansion connector.
GESI - Used for GPIO_PRG0_RGMII_RST
MCAN7_RX GPIO0_24 C_MCASP0_AFSR NA PU Active low I2C0 IO expander interrupt. ('0' - interrupt pending, '1' - no interrupt)(I2C0_IOEXP_INT#)
Note: GPIO only available from Trace/GPMC Mux.
SPI0_D1 GPIO0_55 SEL_SDIO_3V3_1V8n Output PU NA SD Card IO Voltage Selection
('0' - 1.8 V, '1' - 3.3 V)
GPMC0_CLK GPIO0_44 PM_I2C_SEL Output PD NA CP Board - PM I2C Mux selection. ('0' - SOC_I2C2_SCL/SDA -> PM1_SCL/SDA, '1' - SOC_I2C2_SCL/SDA -> PM2_SCL/SDA)
GESI - Boosterpack_GPIO1
RMII1_CRS_DV GPIO0_4 ENET_EXP_INTB Input PU Active low Ethernet Expansion Interrupt. ('0' - interrupt pending, '1' - no interrupt)
MCAN9_TX GPIO0_27 GPIO_RGMII2_INT# Input PU Active low Interrupt function. ('0' - interrupt pending, '1' - no interrupt)
GESI - Used for PRG0_RGMII_INT#
GPIO Expander
I2C0 ADDR: 0x21 P00 USB2.0_MUX_SEL Output PD Active High Signal Mux Control ('0' - USBC, '1' - USB Hub)
I2C0 ADDR: 0x21 P01 CANUART_MUX1_SEL0 Output PD Active High Select line for CANUART MUX1
I2C0 ADDR: 0x21 P02 CANUART_MUX2_SEL0 Output NA Active High Select line for CANUART MUX2
I2C0 ADDR: 0x21 P03 CANUART_MUX_SEL1 Output PU Active High Select line shared for both through CANUART MUX
I2C0 ADDR: 0x21 P04 UART/LIN_MUX_SEL Output PD Active High Signal Mux Control ('0' - UART, '1' - LIN)
I2C0 ADDR: 0x21 P05 TRC_D17/AUDIO_REFCLK_SEL Output PU Active High Signal Mux Control ('0' - Audio_refclk, '1' - TRC_D17)
I2C0 ADDR: 0x21 P06 GPIO_LIN_EN Output PD Active High Enable signal for LIN Transceivers (GESI)
I2C0 ADDR: 0x21 P07 CAN_STB Output PD Active High Standby signals for CAN Transceivers (GESI)