SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 13-39 lists the memory-mapped registers for the ERAD_CRC_REGS registers. All register offset addresses not listed in Table 13-39 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CRC_CURRENT | CRC_CURRENT | Go | |
2h | CRC_SEED | CRC SEED value | Go | |
4h | CRC_QUALIFIER | CRC_QUALIFIER | Go |
Complex bit access types are encoded to fit into small table cells. Table 13-40 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CRC_CURRENT is shown in Figure 13-33 and described in Table 13-41.
Return to the Summary Table.
Current computed CRC value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_CURRENT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC_CURRENT | R | 0h | Reads the current CRC value Reset type: SYSRSn |
CRC_SEED is shown in Figure 13-34 and described in Table 13-42.
Return to the Summary Table.
CRC SEED value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_SEED | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC_SEED | R/W | 0h | CRC Seed Register Reset type: SYSRSn |
CRC_QUALIFIER is shown in Figure 13-35 and described in Table 13-43.
Return to the Summary Table.
CRC compute enable register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_QUALIFIER | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4-0 | CRC_QUALIFIER | R/W | 0h | 0000 = No Qualifier, every valid event is qualified for CRC computation 00001 = CRC Compute Qualified by HWBP_EVENT1 00010 = CRC Compute Qualified by HWBP_EVENT2 00011 = CRC Compute Qualified by HWBP_EVENT3 00100 = CRC Compute Qualified by HWBP_EVENT4 00101 = CRC Compute Qualified by HWBP_EVENT5 00110 = CRC Compute Qualified by HWBP_EVENT6 00111 = CRC Compute Qualified by HWBP_EVENT7 01000 = CRC Compute Qualified by HWBP_EVENT8 01001 = CRC Compute Qualified by HWBP_EVENT_OR1 01010 = CRC Compute Qualified by HWBP_EVENT_OR2 01011 = CRC Compute Qualified by HWBP_EVENT_OR3 01100 = CRC Compute Qualified by HWBP_EVENT_OR4 01101 = CRC Compute Qualified by HWBP_EVENT_AND1 01110 = CRC Compute Qualified by HWBP_EVENT_AND2 01111 = CRC Compute Qualified by HWBP_EVENT_AND3 10000 = CRC Compute Qualified by HWBP_EVENT_AND4 Others = No Qualifier, every valid event is qualified for CRC computation Reset type: SYSRSn |