SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 3-291 lists the memory-mapped registers for the SYS_STATUS_REGS registers. All register offset addresses not listed in Table 3-291 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
10h | SYS_ERR_INT_FLG | Status of interrupts due to multiple different errors in the system. | Go | |
12h | SYS_ERR_INT_CLR | SYS_ERR_INT_FLG clear register | Go | |
14h | SYS_ERR_INT_SET | SYS_ERR_INT_FLG set register | EALLOW | Go |
16h | SYS_ERR_MASK | SYS_ERR_MASK register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-292 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
SYS_ERR_INT_FLG is shown in Figure 3-269 and described in Table 3-293.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | AES_BUS_ERROR | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GINT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | EPG1_INT | R | 0h | 0: EPG1_INT has not fired an interrupt. 1: EPG1_INT has fired an interrupt Reset type: SYSRSn |
10 | AES_BUS_ERROR | R | 0h | 0: AES_BUS_ERROR has not fired an interrupt. 1: AES_BUS_ERROR has fired an interrupt Reset type: SYSRSn |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | GINT | R | 0h | Global Interrupt flag: 0: On any of the flags of SYS_ERR_INT_FLG register being set, SYS_ERR_INT is pulsed and GINT flag would be set 1: No further interrupts would be fired until GINT flag is cleared Reset type: SYSRSn |
SYS_ERR_INT_CLR is shown in Figure 3-270 and described in Table 3-294.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | AES_BUS_ERROR | RESERVED | RESERVED |
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GINT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | EPG1_INT | R-0/W1S | 0h | 0: No effect 1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
10 | AES_BUS_ERROR | R-0/W1S | 0h | 0: No effect 1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | RESERVED | R-0/W1S | 0h | Reserved |
0 | GINT | R-0/W1S | 0h | 0: No effect 1: GINT flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
SYS_ERR_INT_SET is shown in Figure 3-271 and described in Table 3-295.
Return to the Summary Table.
SYS_ERR_INT_FLG set register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | AES_BUS_ERROR | RESERVED | RESERVED |
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R-0/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
23-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | EPG1_INT | R-0/W1S | 0h | 0: No effect 1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
10 | AES_BUS_ERROR | R-0/W1S | 0h | 0: No effect 1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | RESERVED | R-0/W1S | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |
SYS_ERR_MASK is shown in Figure 3-272 and described in Table 3-296.
Return to the Summary Table.
SYS_ERR_MASK register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | AES_BUS_ERROR | RESERVED | RESERVED |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
23-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | EPG1_INT | R/W | 0h | 0: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: EPG1_INT flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
10 | AES_BUS_ERROR | R/W | 0h | 0: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |