SPRUIW9C October   2021  – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.4.4  Power-On Reset (POR)
      5. 3.4.5  Brown-Out-Reset (BOR)
      6. 3.4.6  Debugger Reset (SYSRS)
      7. 3.4.7  Simulate CPU Reset (SIMRESET.CPU1RS)
      8. 3.4.8  Watchdog Reset (WDRS)
      9. 3.4.9  Hardware BIST Reset (HWBISTRS)
      10. 3.4.10 NMI Watchdog Reset (NMIWDRS)
      11. 3.4.11 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
        1. 3.5.5.1 PIE Interrupt Priority
          1. 3.5.5.1.1 Channel Priority
          2. 3.5.5.1.2 Group Priority
      6. 3.5.6 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 CPU HWBIST Error
        5. 3.6.3.5 Software-Forced Error
      4. 3.6.4 CRC Fail
      5. 3.6.5 ERAD NMI
      6. 3.6.6 Illegal Instruction Trap (ITRAP)
      7. 3.6.7 Error Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 Auxiliary Clock Input (AUXCLKIN)
        4. 3.7.1.4 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CAN Bit Clock
        6. 3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
        1. 3.7.7.1 X1/X2 Precondition Circuit
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
      5. 3.10.5 Flash Power-down Considerations
    11. 3.11 Memory Controller Module
      1. 3.11.1  Dedicated RAM (Mx RAM)
      2. 3.11.2  Local Shared RAM (LSx RAM)
      3. 3.11.3  Global Shared RAM (GSx RAM)
      4. 3.11.4  CLA-CPU Message RAM
      5. 3.11.5  CLA-DMA Message RAM
      6. 3.11.6  Access Arbitration
      7. 3.11.7  Access Protection
        1. 3.11.7.1 CPU Fetch Protection
        2. 3.11.7.2 CPU Write Protection
        3. 3.11.7.3 CPU Read Protection
        4. 3.11.7.4 CLA Fetch Protection
        5. 3.11.7.5 CLA Read Protection
        6. 3.11.7.6 CLA Write Protection
        7. 3.11.7.7 HIC Write Protection
        8. 3.11.7.8 DMA Write Protection
      8. 3.11.8  Memory Error Detection and Correction, and Error Handling
        1. 3.11.8.1 Error Detection and Correction
        2. 3.11.8.2 Error Handling
      9. 3.11.9  Application Test Hooks for Error Detection and Correction
      10. 3.11.10 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 Live Firmware Update
      1. 3.13.1 LFU Background
      2. 3.13.2 LFU Switchover Steps
      3. 3.13.3 Device Features Supporting LFU
        1. 3.13.3.1 Multi-Bank Flash
        2. 3.13.3.2 PIE Vector Table Swap
        3. 3.13.3.3 LS0/LS1 RAM Memory Swap
          1. 3.13.3.3.1 Applicability to CLA LFU
      4. 3.13.4 LFU Switchover
      5. 3.13.5 LFU Resources
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 Software
      1. 3.15.1 INTERRUPT Examples
        1. 3.15.1.1 External Interrupts (ExternalInterrupt)
        2. 3.15.1.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.15.1.3 CPU Timer Interrupt Software Prioritization
        4. 3.15.1.4 EPWM Real-Time Interrupt
      2. 3.15.2 SYSCTL Examples
        1. 3.15.2.1 Missing clock detection (MCD)
        2. 3.15.2.2 XCLKOUT (External Clock Output) Configuration
      3. 3.15.3 TIMER Examples
        1. 3.15.3.1 CPU Timers
        2. 3.15.3.2 CPU Timers
      4. 3.15.4 LPM Examples
        1. 3.15.4.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
        2. 3.15.4.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
        3. 3.15.4.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
        4. 3.15.4.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
        5. 3.15.4.5 Low Power Modes: Halt Mode and Wakeup using GPIO
        6. 3.15.4.6 Low Power Modes: Halt Mode and Wakeup
      5. 3.15.5 MEMCFG Examples
        1. 3.15.5.1 Correctable & Uncorrectable Memory Error Handling
      6. 3.15.6 WATCHDOG Examples
        1. 3.15.6.1 Watchdog
    16. 3.16 System Control Registers
      1. 3.16.1  SYSCTRL Base Address Table
      2. 3.16.2  ACCESS_PROTECTION_REGS Registers
      3. 3.16.3  CLK_CFG_REGS Registers
      4. 3.16.4  CPU_SYS_REGS Registers
      5. 3.16.5  CPUTIMER_REGS Registers
      6. 3.16.6  DEV_CFG_REGS Registers
      7. 3.16.7  DMA_CLA_SRC_SEL_REGS Registers
      8. 3.16.8  MEM_CFG_REGS Registers
      9. 3.16.9  MEMORY_ERROR_REGS Registers
      10. 3.16.10 NMI_INTRUPT_REGS Registers
      11. 3.16.11 PERIPH_AC_REGS Registers
      12. 3.16.12 PIE_CTRL_REGS Registers
      13. 3.16.13 SYNC_SOC_REGS Registers
      14. 3.16.14 SYS_STATUS_REGS Registers
      15. 3.16.15 TEST_ERROR_REGS Registers
      16. 3.16.16 UID_REGS Registers
      17. 3.16.17 WD_REGS Registers
      18. 3.16.18 XINT_REGS Registers
      19. 3.16.19 LFU_REGS Registers
      20. 3.16.20 Register to Driverlib Function Mapping
        1. 3.16.20.1 CPUTIMER Registers to Driverlib Functions
        2. 3.16.20.2 DCSM Registers to Driverlib Functions
        3. 3.16.20.3 MEMCFG Registers to Driverlib Functions
        4. 3.16.20.4 NMI Registers to Driverlib Functions
        5. 3.16.20.5 PIE Registers to Driverlib Functions
        6. 3.16.20.6 SYSCTL Registers to Driverlib Functions
        7. 3.16.20.7 WWD Registers to Driverlib Functions
        8. 3.16.20.8 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1  Introduction
    2. 4.2  ROM Related Collateral
    3. 4.3  Device Boot Sequence
    4. 4.4  Device Boot Modes
      1. 4.4.1 Default Boot Modes
      2. 4.4.2 Custom Boot Modes
    5. 4.5  Device Boot Configurations
      1. 4.5.1 Configuring Boot Mode Pins
      2. 4.5.2 Configuring Boot Mode Table Options
      3. 4.5.3 Boot Mode Example Use Cases
        1. 4.5.3.1 Zero Boot Mode Select Pins
        2. 4.5.3.2 One Boot Mode Select Pin
        3. 4.5.3.3 Three Boot Mode Select Pins
    6. 4.6  Device Boot Flow Diagrams
      1. 4.6.1 Boot Flow
      2. 4.6.2 Emulation Boot Flow
      3. 4.6.3 Standalone Boot Flow
    7. 4.7  Device Reset and Exception Handling
      1. 4.7.1 Reset Causes and Handling
      2. 4.7.2 Exceptions and Interrupts Handling
    8. 4.8  Boot ROM Description
      1. 4.8.1  Boot ROM Configuration Registers
        1. 4.8.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.8.2  Entry Points
      3. 4.8.3  Wait Points
      4. 4.8.4  Secure Flash Boot
        1. 4.8.4.1 Secure Flash CPU1 Linker File Example
      5. 4.8.5  Firmware Update (FWU) Flash Boot
      6. 4.8.6  Memory Maps
        1. 4.8.6.1 Boot ROM Memory Maps
        2. 4.8.6.2 CLA Data ROM Memory Maps
        3. 4.8.6.3 Reserved RAM Memory Maps
      7. 4.8.7  ROM Tables
      8. 4.8.8  Boot Modes and Loaders
        1. 4.8.8.1 Boot Modes
          1. 4.8.8.1.1 Flash Boot
          2. 4.8.8.1.2 RAM Boot
          3. 4.8.8.1.3 Wait Boot
        2. 4.8.8.2 Bootloaders
          1. 4.8.8.2.1 SCI Boot Mode
          2. 4.8.8.2.2 SPI Boot Mode
          3. 4.8.8.2.3 I2C Boot Mode
          4. 4.8.8.2.4 Parallel Boot Mode
          5. 4.8.8.2.5 CAN Boot Mode
          6. 4.8.8.2.6 CAN-FD Boot Mode
      9. 4.8.9  GPIO Assignments
      10. 4.8.10 Secure ROM Function APIs
      11. 4.8.11 Clock Initializations
      12. 4.8.12 Boot Status Information
        1. 4.8.12.1 Booting Status
        2. 4.8.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      13. 4.8.13 ROM Version
    9. 4.9  Application Notes for Using the Bootloaders
      1. 4.9.1 Bootloader Data Stream Structure
        1. 4.9.1.1 Data Stream Structure 8-bit
      2. 4.9.2 The C2000 Hex Utility
        1. 4.9.2.1 HEX2000.exe Command Syntax
    10. 4.10 Software
      1. 4.10.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Password Lock
      5. 5.2.5 JTAGLOCK
      6. 5.2.6 Link Pointer and Zone Select
      7. 5.2.7 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Module Controller (FMC)
    4. 6.4  Flash and OTP Memory Power-Down Modes and Wakeup
    5. 6.5  Active Grace Period
    6. 6.6  Flash and OTP Memory Performance
    7. 6.7  Flash Read Interface
      1. 6.7.1 C28x-FMC Flash Read Interface
        1. 6.7.1.1 Standard Read Mode
        2. 6.7.1.2 Prefetch Mode
          1. 6.7.1.2.1 Data Cache
    8. 6.8  Flash Erase and Program
      1. 6.8.1 Erase
      2. 6.8.2 Program
      3. 6.8.3 Verify
    9. 6.9  Error Correction Code (ECC) Protection
      1. 6.9.1 Single-Bit Data Error
      2. 6.9.2 Uncorrectable Error
      3. 6.9.3 SECDED Logic Correctness Check
    10. 6.10 Reserved Locations Within Flash and OTP Memory
    11. 6.11 Migrating an Application from RAM to Flash
    12. 6.12 Procedure to Change the Flash Control Registers
    13. 6.13 Software
      1. 6.13.1 FLASH Examples
        1. 6.13.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        2. 6.13.1.2 Flash ECC Test Mode
        3. 6.13.1.3 Boot Source Code
        4. 6.13.1.4 Erase Source Code
        5. 6.13.1.5 Live DFU Command Functionality
        6. 6.13.1.6 Verify Source Code
        7. 6.13.1.7 SCI Boot Mode Routines
        8. 6.13.1.8 Flash Programming Solution using SCI
    14. 6.14 Flash Registers
      1. 6.14.1 FLASH Base Address Table
      2. 6.14.2 FLASH_CTRL_REGS Registers
      3. 6.14.3 FLASH_ECC_REGS Registers
      4. 6.14.4 FLASH Registers to Driverlib Functions
  9. 7 Control Law Accelerator (CLA)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 CLA Related Collateral
      3. 7.1.3 Block Diagram
    2. 7.2 CLA Interface
      1. 7.2.1 CLA Memory
      2. 7.2.2 CLA Memory Bus
      3. 7.2.3 Shared Peripherals and EALLOW Protection
      4. 7.2.4 CLA Tasks and Interrupt Vectors
    3. 7.3 CLA and CPU Arbitration
      1. 7.3.1 CLA Message RAM
      2. 7.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 7.4 CLA Configuration and Debug
      1. 7.4.1 Building a CLA Application
      2. 7.4.2 Typical CLA Initialization Sequence
      3. 7.4.3 Debugging CLA Code
        1. 7.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 7.4.3.2 Breakpoint Support (MDEBUGSTOP)
      4. 7.4.4 CLA Illegal Opcode Behavior
      5. 7.4.5 Resetting the CLA
    5. 7.5 Pipeline
      1. 7.5.1 Pipeline Overview
      2. 7.5.2 CLA Pipeline Alignment
        1. 7.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       362
        3. 7.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       364
        5. 7.5.2.3 ADC Early Interrupt to CLA Response
      3. 7.5.3 Parallel Instructions
        1. 7.5.3.1 Math Operation with Parallel Load
        2. 7.5.3.2 Multiply with Parallel Add
      4. 7.5.4 CLA Task Execution Latency
    6. 7.6 Software
      1. 7.6.1 CLA Examples
        1. 7.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 7.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        3. 7.6.1.3 CLA background nesting task
        4. 7.6.1.4 Controlling PWM output using CLA
        5. 7.6.1.5 Just-in-time ADC sampling with CLA
        6. 7.6.1.6 Optimal offloading of control algorithms to CLA
        7. 7.6.1.7 Handling shared resources across C28x and CLA
    7. 7.7 Instruction Set
      1. 7.7.1 Instruction Descriptions
      2. 7.7.2 Addressing Modes and Encoding
      3. 7.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 [, CNDF]
        45.       MMOV32 MRa, MRb [, CNDF]
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb[, CNDF]
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD [CNDF]
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb [, CNDF]
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 7.8 CLA Registers
      1. 7.8.1 CLA Base Address Table
      2. 7.8.2 CLA_ONLY_REGS Registers
      3. 7.8.3 CLA_SOFTINT_REGS Registers
      4. 7.8.4 CLA_REGS Registers
      5. 7.8.5 CLA Registers to Driverlib Functions
  10. 8 Dual-Clock Comparator (DCC)
    1. 8.1 Introduction
      1. 8.1.1 Features
      2. 8.1.2 Block Diagram
    2. 8.2 Module Operation
      1. 8.2.1 Configuring DCC Counters
      2. 8.2.2 Single-Shot Measurement Mode
      3. 8.2.3 Continuous Monitoring Mode
      4. 8.2.4 Error Conditions
    3. 8.3 Interrupts
    4. 8.4 Software
      1. 8.4.1 DCC Examples
        1. 8.4.1.1 DCC Single shot Clock verification
        2. 8.4.1.2 DCC Single shot Clock measurement
        3. 8.4.1.3 DCC Continuous clock monitoring
        4. 8.4.1.4 DCC Continuous clock monitoring
        5. 8.4.1.5 DCC Detection of clock failure
    5. 8.5 DCC Registers
      1. 8.5.1 DCC Base Address Table
      2. 8.5.2 DCC_REGS Registers
      3. 8.5.3 DCC Registers to Driverlib Functions
  11. 9 Background CRC-32 (BGCRC)
    1. 9.1 Introduction
      1. 9.1.1 BGCRC Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Block Diagram
      4. 9.1.4 Memory Wait States and Memory Map
    2. 9.2 Functional Description
      1. 9.2.1 Data Read Unit
      2. 9.2.2 CRC-32 Compute Unit
      3. 9.2.3 CRC Notification Unit
        1. 9.2.3.1 CPU Interrupt, CLA Task and NMI
      4. 9.2.4 Operating Modes
        1. 9.2.4.1 CRC Mode
        2. 9.2.4.2 Scrub Mode
      5. 9.2.5 BGCRC Watchdog
      6. 9.2.6 Hardware and Software Faults Protection
    3. 9.3 Application of the BGCRC
      1. 9.3.1 Software Configuration
      2. 9.3.2 Decision on Error Response Severity
      3. 9.3.3 Decision of Controller for CLA_CRC
      4. 9.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 9.3.5 BGCRC Execution
      6. 9.3.6 Debug/Error Response for BGCRC Errors
      7. 9.3.7 BGCRC Golden CRC-32 Value Computation
    4. 9.4 Software
      1. 9.4.1 BGCRC Examples
        1. 9.4.1.1 BGCRC CPU Interrupt Example
        2. 9.4.1.2 BGCRC Example with Watchdog and Lock
        3. 9.4.1.3 CLA-BGCRC Example in CRC mode
        4. 9.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 9.5 BGCRC Registers
      1. 9.5.1 BGCRC Base Address Table
      2. 9.5.2 BGCRC_REGS Registers
      3. 9.5.3 BGCRC Registers to Driverlib Functions
  12. 10General-Purpose Input/Output (GPIO)
    1. 10.1  Introduction
      1. 10.1.1 GPIO Related Collateral
    2. 10.2  Configuration Overview
    3. 10.3  Digital Inputs on ADC Pins (AIOs)
    4. 10.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 10.5  Digital General-Purpose I/O Control
    6. 10.6  Input Qualification
      1. 10.6.1 No Synchronization (Asynchronous Input)
      2. 10.6.2 Synchronization to SYSCLKOUT Only
      3. 10.6.3 Qualification Using a Sampling Window
    7. 10.7  GPIO and Peripheral Muxing
      1. 10.7.1 GPIO Muxing
      2. 10.7.2 Peripheral Muxing
    8. 10.8  Internal Pullup Configuration Requirements
    9. 10.9  Software
      1. 10.9.1 GPIO Examples
        1. 10.9.1.1 Device GPIO Setup
        2. 10.9.1.2 Device GPIO Toggle
        3. 10.9.1.3 Device GPIO Interrupt
        4. 10.9.1.4 External Interrupt (XINT)
      2. 10.9.2 LED Examples
    10. 10.10 GPIO Registers
      1. 10.10.1 GPIO Base Address Table
      2. 10.10.2 GPIO_CTRL_REGS Registers
      3. 10.10.3 GPIO_DATA_REGS Registers
      4. 10.10.4 GPIO_DATA_READ_REGS Registers
      5. 10.10.5 GPIO Registers to Driverlib Functions
  13. 11Crossbar (X-BAR)
    1. 11.1 Input X-BAR and CLB Input X-BAR
      1. 11.1.1 CLB Input X-BAR
    2. 11.2 ePWM, CLB, and GPIO Output X-BAR
      1. 11.2.1 ePWM X-BAR
        1. 11.2.1.1 ePWM X-BAR Architecture
      2. 11.2.2 CLB X-BAR
        1. 11.2.2.1 CLB X-BAR Architecture
      3. 11.2.3 GPIO Output X-BAR
        1. 11.2.3.1 GPIO Output X-BAR Architecture
      4. 11.2.4 CLB Output X-BAR
        1. 11.2.4.1 CLB Output X-BAR Architecture
      5. 11.2.5 X-BAR Flags
    3. 11.3 XBAR Registers
      1. 11.3.1 XBAR Base Address Table
      2. 11.3.2 INPUT_XBAR_REGS Registers
      3. 11.3.3 XBAR_REGS Registers
      4. 11.3.4 EPWM_XBAR_REGS Registers
      5. 11.3.5 CLB_XBAR_REGS Registers
      6. 11.3.6 OUTPUT_XBAR_REGS Registers
      7. 11.3.7 Register to Driverlib Function Mapping
        1. 11.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 11.3.7.2 XBAR Registers to Driverlib Functions
        3. 11.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 11.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 11.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  14. 12Direct Memory Access (DMA)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Architecture
      1. 12.2.1 Peripheral Interrupt Event Trigger Sources
      2. 12.2.2 DMA Bus
    3. 12.3 Address Pointer and Transfer Control
    4. 12.4 Pipeline Timing and Throughput
    5. 12.5 CPU and CLA Arbitration
    6. 12.6 Channel Priority
      1. 12.6.1 Round-Robin Mode
      2. 12.6.2 Channel 1 High-Priority Mode
    7. 12.7 Overrun Detection Feature
    8. 12.8 Software
      1. 12.8.1 DMA Examples
        1. 12.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 12.8.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 12.9 DMA Registers
      1. 12.9.1 DMA Base Address Table
      2. 12.9.2 DMA_REGS Registers
      3. 12.9.3 DMA_CH_REGS Registers
      4. 12.9.4 DMA Registers to Driverlib Functions
  15. 13Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 13.1 Introduction
      1. 13.1.1 ERAD Related Collateral
    2. 13.2 Enhanced Bus Comparator Unit
      1. 13.2.1 Enhanced Bus Comparator Unit Operations
      2. 13.2.2 Event Masking and Exporting
    3. 13.3 System Event Counter Unit
      1. 13.3.1 System Event Counter Modes
        1. 13.3.1.1 Counting Active Levels Versus Edges
        2. 13.3.1.2 Max Mode
        3. 13.3.1.3 Cumulative Mode
        4. 13.3.1.4 Input Signal Selection
      2. 13.3.2 Reset on Event
      3. 13.3.3 Operation Conditions
    4. 13.4 ERAD Ownership, Initialization and Reset
    5. 13.5 ERAD Programming Sequence
      1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 13.5.2 Timer and Counter Programming Sequence
    6. 13.6 Cyclic Redundancy Check Unit
      1. 13.6.1 CRC Unit Qualifier
      2. 13.6.2 CRC Unit Programming Sequence
    7. 13.7 Program Counter Trace
      1. 13.7.1 Functional Block Diagram
      2. 13.7.2 Trace Qualification Modes
        1. 13.7.2.1 Trace Qualifier Input Signals
      3. 13.7.3 Trace Memory
      4. 13.7.4 Trace Input Signal Conditioning
      5. 13.7.5 PC Trace Software Operation
      6. 13.7.6 Trace Operation in Debug Mode
    8. 13.8 Software
      1. 13.8.1 ERAD Examples
        1. 13.8.1.1  ERAD Profiling Interrupts
        2. 13.8.1.2  ERAD Profile Function
        3. 13.8.1.3  ERAD Profile Function
        4. 13.8.1.4  ERAD HWBP Monitor Program Counter
        5. 13.8.1.5  ERAD HWBP Monitor Program Counter
        6. 13.8.1.6  ERAD Profile Function
        7. 13.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 13.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 13.8.1.9  ERAD Stack Overflow
        10. 13.8.1.10 ERAD Profile Interrupts CLA
        11. 13.8.1.11 ERAD Profiling Interrupts
        12. 13.8.1.12 ERAD Profiling Interrupts
        13. 13.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 13.8.1.14 ERAD INTERRUPT ORDER
        15. 13.8.1.15 ERAD AND CLB
        16. 13.8.1.16 ERAD PWM PROTECTION
    9. 13.9 ERAD Registers
      1. 13.9.1 ERAD Base Address Table
      2. 13.9.2 ERAD_GLOBAL_REGS Registers
      3. 13.9.3 ERAD_HWBP_REGS Registers
      4. 13.9.4 ERAD_COUNTER_REGS Registers
      5. 13.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 13.9.6 ERAD_CRC_REGS Registers
      7. 13.9.7 ERAD Registers to Driverlib Functions
  16. 14Host Interface Controller (HIC)
    1. 14.1 Introduction
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
      3. 14.1.3 HIC Related Collateral
    2. 14.2 Functional Description
      1. 14.2.1 Memory Map
      2. 14.2.2 Connections
        1. 14.2.2.1 Functions of the Connections
      3. 14.2.3 Interrupts and Triggers
    3. 14.3 Operation
      1. 14.3.1 Mailbox Access Mode Overview
        1. 14.3.1.1 Mailbox Access Mode Operation
        2. 14.3.1.2 Configuring HIC Registers With External Host
        3. 14.3.1.3 Mailbox Access Mode Read/Write
      2. 14.3.2 Direct Access Mode Overview
        1. 14.3.2.1 Direct Access Mode Operation
        2. 14.3.2.2 Direct Access Mode Read/Write
      3. 14.3.3 Controlling Reads and Writes
        1. 14.3.3.1 Single-Pin Read/Write Mode (nOE/RnW Pin)
        2. 14.3.3.2 Dual-Pin Read/Write Mode (nOE and nWE Pins)
      4. 14.3.4 Data Lines, Data Width, Data Packing and Unpacking
      5. 14.3.5 Address Translation
      6. 14.3.6 Access Errors
      7. 14.3.7 Security
      8. 14.3.8 HIC Usage
    4. 14.4 Usage Scenarious for Reduced Number of Pins
    5. 14.5 Software
      1. 14.5.1 HIC Examples
        1. 14.5.1.1 HIC 16-bit Memory Access Example
        2. 14.5.1.2 HIC 8-bit Memory Access Example
        3. 14.5.1.3 HIC 16-bit Memory Access FSI Example
    6. 14.6 HIC Registers
      1. 14.6.1 HIC Base Address Table
      2. 14.6.2 HIC_CFG_REGS Registers
      3. 14.6.3 HIC Registers to Driverlib Functions
  17. 15Analog Subsystem
    1. 15.1 Introduction
      1. 15.1.1 Features
      2. 15.1.2 Block Diagram
    2. 15.2 Optimizing Power-Up Time
    3. 15.3 Digital Inputs on ADC Pins (AIOs)
    4. 15.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5 Analog Pins and Internal Connections
    6. 15.6 Analog Subsystem Registers
      1. 15.6.1 ASBSYS Base Address Table
      2. 15.6.2 ANALOG_SUBSYS_REGS Registers
      3. 15.6.3 ASYSCTL Registers to Driverlib Functions
  18. 16Analog-to-Digital Converter (ADC)
    1. 16.1  Introduction
      1. 16.1.1 ADC Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
    2. 16.2  ADC Configurability
      1. 16.2.1 Clock Configuration
      2. 16.2.2 Resolution
      3. 16.2.3 Voltage Reference
        1. 16.2.3.1 External Reference Mode
        2. 16.2.3.2 Internal Reference Mode
        3. 16.2.3.3 Selecting Reference Mode
      4. 16.2.4 Signal Mode
      5. 16.2.5 Expected Conversion Results
      6. 16.2.6 Interpreting Conversion Results
    3. 16.3  SOC Principle of Operation
      1. 16.3.1 SOC Configuration
      2. 16.3.2 Trigger Operation
      3. 16.3.3 ADC Acquisition (Sample and Hold) Window
      4. 16.3.4 ADC Input Models
      5. 16.3.5 Channel Selection
    4. 16.4  SOC Configuration Examples
      1. 16.4.1 Single Conversion from ePWM Trigger
      2. 16.4.2 Oversampled Conversion from ePWM Trigger
      3. 16.4.3 Multiple Conversions from CPU Timer Trigger
      4. 16.4.4 Software Triggering of SOCs
    5. 16.5  ADC Conversion Priority
    6. 16.6  Burst Mode
      1. 16.6.1 Burst Mode Example
      2. 16.6.2 Burst Mode Priority Example
    7. 16.7  EOC and Interrupt Operation
      1. 16.7.1 Interrupt Overflow
      2. 16.7.2 Continue to Interrupt Mode
      3. 16.7.3 Early Interrupt Configuration Mode
    8. 16.8  Post-Processing Blocks
      1. 16.8.1 PPB Offset Correction
      2. 16.8.2 PPB Error Calculation
      3. 16.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 16.8.4 PPB Sample Delay Capture
    9. 16.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 16.9.1 Implementation
      2. 16.9.2 Detecting an Open Input Pin
      3. 16.9.3 Detecting a Shorted Input Pin
    10. 16.10 Power-Up Sequence
    11. 16.11 ADC Calibration
      1. 16.11.1 ADC Zero Offset Calibration
    12. 16.12 ADC Timings
      1. 16.12.1 ADC Timing Diagrams
    13. 16.13 Additional Information
      1. 16.13.1 Ensuring Synchronous Operation
        1. 16.13.1.1 Basic Synchronous Operation
        2. 16.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 16.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 16.13.1.4 Non-overlapping Conversions
      2. 16.13.2 Choosing an Acquisition Window Duration
      3. 16.13.3 Achieving Simultaneous Sampling
      4. 16.13.4 Result Register Mapping
      5. 16.13.5 Internal Temperature Sensor
      6. 16.13.6 Designing an External Reference Circuit
      7. 16.13.7 ADC-DAC Loopback Testing
      8. 16.13.8 Internal Test Mode
      9. 16.13.9 ADC Gain and Offset Calibration
    14. 16.14 Software
      1. 16.14.1 ADC Examples
        1. 16.14.1.1  ADC Software Triggering
        2. 16.14.1.2  ADC ePWM Triggering
        3. 16.14.1.3  ADC Temperature Sensor Conversion
        4. 16.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 16.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 16.14.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 16.14.1.7  ADC PPB Offset (adc_ppb_offset)
        8. 16.14.1.8  ADC PPB Limits (adc_ppb_limits)
        9. 16.14.1.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 16.14.1.10 ADC ePWM Triggering Multiple SOC
        11. 16.14.1.11 ADC Burst Mode
        12. 16.14.1.12 ADC Burst Mode Oversampling
        13. 16.14.1.13 ADC SOC Oversampling
        14. 16.14.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
        15. 16.14.1.15 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 16.15 ADC Registers
      1. 16.15.1 ADC Base Address Table
      2. 16.15.2 ADC_RESULT_REGS Registers
      3. 16.15.3 ADC_REGS Registers
      4. 16.15.4 ADC Registers to Driverlib Functions
  19. 17Buffered Digital-to-Analog Converter (DAC)
    1. 17.1 Introduction
      1. 17.1.1 DAC Related Collateral
      2. 17.1.2 Features
      3. 17.1.3 Block Diagram
    2. 17.2 Using the DAC
      1. 17.2.1 Initialization Sequence
      2. 17.2.2 DAC Offset Adjustment
      3. 17.2.3 EPWMSYNCPER Signal
    3. 17.3 Lock Registers
    4. 17.4 Software
      1. 17.4.1 DAC Examples
        1. 17.4.1.1 Buffered DAC Enable
        2. 17.4.1.2 Buffered DAC Random
        3. 17.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 17.5 DAC Registers
      1. 17.5.1 DAC Base Address Table
      2. 17.5.2 DAC_REGS Registers
      3. 17.5.3 DAC Registers to Driverlib Functions
  20. 18Comparator Subsystem (CMPSS)
    1. 18.1 Introduction
      1. 18.1.1 CMPSS Related Collateral
      2. 18.1.2 Features
      3. 18.1.3 Block Diagram
    2. 18.2 Comparator
    3. 18.3 Reference DAC
    4. 18.4 Ramp Generator
      1. 18.4.1 Ramp Generator Overview
      2. 18.4.2 Ramp Generator Behavior
      3. 18.4.3 Ramp Generator Behavior at Corner Cases
    5. 18.5 Digital Filter
      1. 18.5.1 Filter Initialization Sequence
    6. 18.6 Using the CMPSS
      1. 18.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 18.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 18.6.3 Calibrating the CMPSS
      4. 18.6.4 Enabling and Disabling the CMPSS Clock
    7. 18.7 Software
      1. 18.7.1 CMPSS Examples
        1. 18.7.1.1 CMPSS Asynchronous Trip
        2. 18.7.1.2 CMPSS Digital Filter Configuration
    8. 18.8 CMPSS Registers
      1. 18.8.1 CMPSS Base Address Table
      2. 18.8.2 CMPSS_REGS Registers
      3. 18.8.3 CMPSS Registers to Driverlib Functions
  21. 19Sigma Delta Filter Module (SDFM)
    1. 19.1  Introduction
      1. 19.1.1 SDFM Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Block Diagram
    2. 19.2  Configuring Device Pins
    3. 19.3  Input Qualification
    4. 19.4  Input Control Unit
    5. 19.5  SDFM Clock Control
    6. 19.6  Sinc Filter
      1. 19.6.1 Data Rate and Latency of the Sinc Filter
    7. 19.7  Data (Primary) Filter Unit
      1. 19.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 19.7.2 Data FIFO
      3. 19.7.3 SDSYNC Event
    8. 19.8  Comparator (Secondary) Filter Unit
      1. 19.8.1 Higher Threshold (HLT) Comparators
      2. 19.8.2 Lower Threshold (LLT) Comparators
      3. 19.8.3 Digital Filter
    9. 19.9  Theoretical SDFM Filter Output
    10. 19.10 Interrupt Unit
      1. 19.10.1 SDFM (SDyERR) Interrupt Sources
      2. 19.10.2 Data Ready (DRINT) Interrupt Sources
    11. 19.11 Software
      1. 19.11.1 SDFM Examples
        1. 19.11.1.1 SDFM Filter Sync CPU
        2. 19.11.1.2 SDFM Filter Sync CLA
        3. 19.11.1.3 SDFM Filter Sync DMA
        4. 19.11.1.4 SDFM PWM Sync
        5. 19.11.1.5 SDFM Type 1 Filter FIFO
        6. 19.11.1.6 SDFM Filter Sync CLA
    12. 19.12 SDFM Registers
      1. 19.12.1 SDFM Base Address Table
      2. 19.12.2 SDFM_REGS Registers
      3. 19.12.3 SDFM Registers to Driverlib Functions
  22. 20Enhanced Pulse Width Modulator (ePWM)
    1. 20.1  Introduction
      1. 20.1.1 EPWM Related Collateral
      2. 20.1.2 Submodule Overview
    2. 20.2  Configuring Device Pins
    3. 20.3  ePWM Modules Overview
    4. 20.4  Time-Base (TB) Submodule
      1. 20.4.1 Purpose of the Time-Base Submodule
      2. 20.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 20.4.3 Calculating PWM Period and Frequency
        1. 20.4.3.1 Time-Base Period Shadow Register
        2. 20.4.3.2 Time-Base Clock Synchronization
        3. 20.4.3.3 Time-Base Counter Synchronization
        4. 20.4.3.4 ePWM SYNC Selection
      4. 20.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 20.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 20.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 20.4.7 Global Load
        1. 20.4.7.1 Global Load Pulse Pre-Scalar
        2. 20.4.7.2 One-Shot Load Mode
        3. 20.4.7.3 One-Shot Sync Mode
    5. 20.5  Counter-Compare (CC) Submodule
      1. 20.5.1 Purpose of the Counter-Compare Submodule
      2. 20.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 20.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 20.5.4 Count Mode Timing Waveforms
    6. 20.6  Action-Qualifier (AQ) Submodule
      1. 20.6.1 Purpose of the Action-Qualifier Submodule
      2. 20.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 20.6.3 Action-Qualifier Event Priority
      4. 20.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 20.6.5 Configuration Requirements for Common Waveforms
    7. 20.7  Dead-Band Generator (DB) Submodule
      1. 20.7.1 Purpose of the Dead-Band Submodule
      2. 20.7.2 Dead-band Submodule Additional Operating Modes
      3. 20.7.3 Operational Highlights for the Dead-Band Submodule
    8. 20.8  PWM Chopper (PC) Submodule
      1. 20.8.1 Purpose of the PWM Chopper Submodule
      2. 20.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 20.8.3 Waveforms
        1. 20.8.3.1 One-Shot Pulse
        2. 20.8.3.2 Duty Cycle Control
    9. 20.9  Trip-Zone (TZ) Submodule
      1. 20.9.1 Purpose of the Trip-Zone Submodule
      2. 20.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 20.9.2.1 Trip-Zone Configurations
      3. 20.9.3 Generating Trip Event Interrupts
    10. 20.10 Event-Trigger (ET) Submodule
      1. 20.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 20.11 Digital Compare (DC) Submodule
      1. 20.11.1 Purpose of the Digital Compare Submodule
      2. 20.11.2 Enhanced Trip Action Using CMPSS
      3. 20.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 20.11.4 Operation Highlights of the Digital Compare Submodule
        1. 20.11.4.1 Digital Compare Events
        2. 20.11.4.2 Event Filtering
        3. 20.11.4.3 Valley Switching
    12. 20.12 ePWM Crossbar (X-BAR)
    13. 20.13 Applications to Power Topologies
      1. 20.13.1  Overview of Multiple Modules
      2. 20.13.2  Key Configuration Capabilities
      3. 20.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 20.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 20.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 20.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 20.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 20.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 20.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 20.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 20.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 20.14 Register Lock Protection
    15. 20.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 20.15.1 Operational Description of HRPWM
        1. 20.15.1.1 Controlling the HRPWM Capabilities
        2. 20.15.1.2 HRPWM Source Clock
        3. 20.15.1.3 Configuring the HRPWM
        4. 20.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 20.15.1.5 Principle of Operation
          1. 20.15.1.5.1 Edge Positioning
          2. 20.15.1.5.2 Scaling Considerations
          3. 20.15.1.5.3 Duty Cycle Range Limitation
          4. 20.15.1.5.4 High-Resolution Period
            1. 20.15.1.5.4.1 High-Resolution Period Configuration
        6. 20.15.1.6 Deadband High-Resolution Operation
        7. 20.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 20.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 20.15.1.8.1 #Defines for HRPWM Header Files
          2. 20.15.1.8.2 Implementing a Simple Buck Converter
            1. 20.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 20.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 20.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 20.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 20.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 20.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 20.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 20.15.2.2 Software Usage
          1. 20.15.2.2.1 A Sample of How to Add "Include" Files
          2.        963
          3. 20.15.2.2.2 Declaring an Element
          4.        965
          5. 20.15.2.2.3 Initializing With a Scale Factor Value
          6.        967
          7. 20.15.2.2.4 SFO Function Calls
    16. 20.16 Software
      1. 20.16.1 EPWM Examples
        1. 20.16.1.1  ePWM Trip Zone
        2. 20.16.1.2  ePWM Up Down Count Action Qualifier
        3. 20.16.1.3  ePWM Synchronization
        4. 20.16.1.4  ePWM Digital Compare
        5. 20.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 20.16.1.6  ePWM Valley Switching
        7. 20.16.1.7  ePWM Digital Compare Edge Filter
        8. 20.16.1.8  ePWM Deadband
        9. 20.16.1.9  ePWM DMA
        10. 20.16.1.10 ePWM Chopper
        11. 20.16.1.11 EPWM Configure Signal
        12. 20.16.1.12 Realization of Monoshot mode
        13. 20.16.1.13 EPWM Action Qualifier (epwm_up_aq)
      2. 20.16.2 HRPWM Examples
        1. 20.16.2.1 HRPWM Duty Control with SFO
        2. 20.16.2.2 HRPWM Slider
        3. 20.16.2.3 HRPWM Period Control
        4. 20.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 20.16.2.5 HRPWM Slider Test
        6. 20.16.2.6 HRPWM Duty Up Count
        7. 20.16.2.7 HRPWM Period Up-Down Count
    17. 20.17 ePWM Registers
      1. 20.17.1 EPWM Base Address Table
      2. 20.17.2 EPWM_REGS Registers
      3. 20.17.3 Register to Driverlib Function Mapping
        1. 20.17.3.1 EPWM Registers to Driverlib Functions
        2. 20.17.3.2 HRPWM Registers to Driverlib Functions
  23. 21Enhanced Capture (eCAP)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 ECAP Related Collateral
    2. 21.2 Description
    3. 21.3 Configuring Device Pins for the eCAP
    4. 21.4 Capture and APWM Operating Mode
    5. 21.5 Capture Mode Description
      1. 21.5.1  Event Prescaler
      2. 21.5.2  Edge Polarity Select and Qualifier
      3. 21.5.3  Continuous/One-Shot Control
      4. 21.5.4  32-Bit Counter and Phase Control
      5. 21.5.5  CAP1-CAP4 Registers
      6. 21.5.6  eCAP Synchronization
        1. 21.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 21.5.7  Interrupt Control
      8. 21.5.8  DMA Interrupt
      9. 21.5.9  Shadow Load and Lockout Control
      10. 21.5.10 APWM Mode Operation
    6. 21.6 Application of the eCAP Module
      1. 21.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 21.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 21.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 21.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 21.7 Application of the APWM Mode
      1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 21.8 Software
      1. 21.8.1 ECAP Examples
        1. 21.8.1.1 eCAP APWM Example
        2. 21.8.1.2 eCAP Capture PWM Example
        3. 21.8.1.3 eCAP APWM Phase-shift Example
        4. 21.8.1.4 eCAP Software Sync Example
    9. 21.9 eCAP Registers
      1. 21.9.1 ECAP Base Address Table
      2. 21.9.2 ECAP_REGS Registers
      3. 21.9.3 ECAP Registers to Driverlib Functions
  24. 22High Resolution Capture (HRCAP)
    1. 22.1 Introduction
      1. 22.1.1 HRCAP Related Collateral
      2. 22.1.2 Features
      3. 22.1.3 Description
    2. 22.2 Operational Details
      1. 22.2.1 HRCAP Clocking
      2. 22.2.2 HRCAP Initialization Sequence
      3. 22.2.3 HRCAP Interrupts
      4. 22.2.4 HRCAP Calibration
        1. 22.2.4.1 Applying the Scale Factor
    3. 22.3 Known Exceptions
    4. 22.4 Software
      1. 22.4.1 HRCAP Examples
        1. 22.4.1.1 HRCAP Capture and Calibration Example
    5. 22.5 HRCAP Registers
      1. 22.5.1 HRCAP Base Address Table
      2. 22.5.2 HRCAP_REGS Registers
      3. 22.5.3 HRCAP Registers to Driverlib Functions
  25. 23Enhanced Quadrature Encoder Pulse (eQEP)
    1. 23.1  Introduction
      1. 23.1.1 EQEP Related Collateral
    2. 23.2  Configuring Device Pins
    3. 23.3  Description
      1. 23.3.1 EQEP Inputs
      2. 23.3.2 Functional Description
      3. 23.3.3 eQEP Memory Map
    4. 23.4  Quadrature Decoder Unit (QDU)
      1. 23.4.1 Position Counter Input Modes
        1. 23.4.1.1 Quadrature Count Mode
        2. 23.4.1.2 Direction-Count Mode
        3. 23.4.1.3 Up-Count Mode
        4. 23.4.1.4 Down-Count Mode
      2. 23.4.2 eQEP Input Polarity Selection
      3. 23.4.3 Position-Compare Sync Output
    5. 23.5  Position Counter and Control Unit (PCCU)
      1. 23.5.1 Position Counter Operating Modes
        1. 23.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 23.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 23.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 23.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 23.5.2 Position Counter Latch
        1. 23.5.2.1 Index Event Latch
        2. 23.5.2.2 Strobe Event Latch
      3. 23.5.3 Position Counter Initialization
      4. 23.5.4 eQEP Position-compare Unit
    6. 23.6  eQEP Edge Capture Unit
    7. 23.7  eQEP Watchdog
    8. 23.8  eQEP Unit Timer Base
    9. 23.9  QMA Module
      1. 23.9.1 Modes of Operation
        1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 23.9.2 Interrupt and Error Generation
    10. 23.10 eQEP Interrupt Structure
    11. 23.11 Software
      1. 23.11.1 EQEP Examples
        1. 23.11.1.1 Frequency Measurement Using eQEP
        2. 23.11.1.2 Position and Speed Measurement Using eQEP
        3. 23.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 23.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 23.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 23.12 eQEP Registers
      1. 23.12.1 EQEP Base Address Table
      2. 23.12.2 EQEP_REGS Registers
      3. 23.12.3 EQEP Registers to Driverlib Functions
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Introduction
      1. 24.1.1 Features
      2. 24.1.2 SPI Related Collateral
      3. 24.1.3 Block Diagram
    2. 24.2 System-Level Integration
      1. 24.2.1 SPI Module Signals
      2. 24.2.2 Configuring Device Pins
        1. 24.2.2.1 GPIOs Required for High-Speed Mode
      3. 24.2.3 SPI Interrupts
      4. 24.2.4 DMA Support
    3. 24.3 SPI Operation
      1. 24.3.1 Introduction to Operation
      2. 24.3.2 Master Mode
      3. 24.3.3 Slave Mode
      4. 24.3.4 Data Format
        1. 24.3.4.1 Transmission of Bit from SPIRXBUF
      5. 24.3.5 Baud Rate Selection
        1. 24.3.5.1 Baud Rate Determination
        2. 24.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 24.3.6 SPI Clocking Schemes
      7. 24.3.7 SPI FIFO Description
      8. 24.3.8 SPI DMA Transfers
        1. 24.3.8.1 Transmitting Data Using SPI with DMA
        2. 24.3.8.2 Receiving Data Using SPI with DMA
    4. 24.4 Programming Procedure
      1. 24.4.1 Initialization Upon Reset
      2. 24.4.2 Configuring the SPI
      3. 24.4.3 Data Transfer Example
    5. 24.5 Software
      1. 24.5.1 SPI Examples
        1. 24.5.1.1 SPI Digital Loopback
        2. 24.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 24.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 24.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 24.5.1.5 SPI Digital Loopback with DMA
        6. 24.5.1.6 SPI EEPROM
        7. 24.5.1.7 SPI DMA EEPROM
    6. 24.6 SPI Registers
      1. 24.6.1 SPI Base Address Table
      2. 24.6.2 SPI_REGS Registers
      3. 24.6.3 SPI Registers to Driverlib Functions
  27. 25Serial Communications Interface (SCI)
    1. 25.1  Introduction
      1. 25.1.1 Features
      2. 25.1.2 SCI Related Collateral
      3. 25.1.3 Block Diagram
    2. 25.2  Architecture
    3. 25.3  SCI Module Signal Summary
    4. 25.4  Configuring Device Pins
    5. 25.5  Multiprocessor and Asynchronous Communication Modes
    6. 25.6  SCI Programmable Data Format
    7. 25.7  SCI Multiprocessor Communication
      1. 25.7.1 Recognizing the Address Byte
      2. 25.7.2 Controlling the SCI TX and RX Features
      3. 25.7.3 Receipt Sequence
    8. 25.8  Idle-Line Multiprocessor Mode
      1. 25.8.1 Idle-Line Mode Steps
      2. 25.8.2 Block Start Signal
      3. 25.8.3 Wake-Up Temporary (WUT) Flag
        1. 25.8.3.1 Sending a Block Start Signal
      4. 25.8.4 Receiver Operation
    9. 25.9  Address-Bit Multiprocessor Mode
      1. 25.9.1 Sending an Address
    10. 25.10 SCI Communication Format
      1. 25.10.1 Receiver Signals in Communication Modes
      2. 25.10.2 Transmitter Signals in Communication Modes
    11. 25.11 SCI Port Interrupts
      1. 25.11.1 Break Detect
    12. 25.12 SCI Baud Rate Calculations
    13. 25.13 SCI Enhanced Features
      1. 25.13.1 SCI FIFO Description
      2. 25.13.2 SCI Auto-Baud
      3. 25.13.3 Autobaud-Detect Sequence
    14. 25.14 Software
      1. 25.14.1 SCI Examples
        1. 25.14.1.1 Tune Baud Rate via UART Example
        2. 25.14.1.2 SCI FIFO Digital Loop Back
        3. 25.14.1.3 SCI Digital Loop Back with Interrupts
        4. 25.14.1.4 SCI Echoback
        5. 25.14.1.5 stdout redirect example
    15. 25.15 SCI Registers
      1. 25.15.1 SCI Base Address Table
      2. 25.15.2 SCI_REGS Registers
      3. 25.15.3 SCI Registers to Driverlib Functions
  28. 26Inter-Integrated Circuit Module (I2C)
    1. 26.1 Introduction
      1. 26.1.1 I2C Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Features Not Supported
      4. 26.1.4 Functional Overview
      5. 26.1.5 Clock Generation
      6. 26.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 26.1.6.1 Formula for the Master Clock Period
    2. 26.2 Configuring Device Pins
    3. 26.3 I2C Module Operational Details
      1. 26.3.1  Input and Output Voltage Levels
      2. 26.3.2  Selecting Pullup Resistors
      3. 26.3.3  Data Validity
      4. 26.3.4  Operating Modes
      5. 26.3.5  I2C Module START and STOP Conditions
      6. 26.3.6  Non-repeat Mode versus Repeat Mode
      7. 26.3.7  Serial Data Formats
        1. 26.3.7.1 7-Bit Addressing Format
        2. 26.3.7.2 10-Bit Addressing Format
        3. 26.3.7.3 Free Data Format
        4. 26.3.7.4 Using a Repeated START Condition
      8. 26.3.8  Clock Synchronization
      9. 26.3.9  Arbitration
      10. 26.3.10 Digital Loopback Mode
      11. 26.3.11 NACK Bit Generation
    4. 26.4 Interrupt Requests Generated by the I2C Module
      1. 26.4.1 Basic I2C Interrupt Requests
      2. 26.4.2 I2C FIFO Interrupts
    5. 26.5 Resetting or Disabling the I2C Module
    6. 26.6 Software
      1. 26.6.1 I2C Examples
        1. 26.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 26.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 26.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 26.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 26.6.1.5 I2C EEPROM
        6. 26.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 26.6.1.7 I2C EEPROM
        8. 26.6.1.8 I2C controller target communication using FIFO interrupts
        9. 26.6.1.9 I2C EEPROM
    7. 26.7 I2C Registers
      1. 26.7.1 I2C Base Address Table
      2. 26.7.2 I2C_REGS Registers
      3. 26.7.3 I2C Registers to Driverlib Functions
  29. 27Power Management Bus Module (PMBus)
    1. 27.1 Introduction
      1. 27.1.1 PMBUS Related Collateral
      2. 27.1.2 Features
      3. 27.1.3 Block Diagram
    2. 27.2 Configuring Device Pins
    3. 27.3 Slave Mode Operation
      1. 27.3.1 Configuration
      2. 27.3.2 Message Handling
        1. 27.3.2.1  Quick Command
        2. 27.3.2.2  Send Byte
        3. 27.3.2.3  Receive Byte
        4. 27.3.2.4  Write Byte and Write Word
        5. 27.3.2.5  Read Byte and Read Word
        6. 27.3.2.6  Process Call
        7. 27.3.2.7  Block Write
        8. 27.3.2.8  Block Read
        9. 27.3.2.9  Block Write-Block Read Process Call
        10. 27.3.2.10 Alert Response
        11. 27.3.2.11 Extended Command
        12. 27.3.2.12 Group Command
    4. 27.4 Master Mode Operation
      1. 27.4.1 Configuration
      2. 27.4.2 Message Handling
        1. 27.4.2.1  Quick Command
        2. 27.4.2.2  Send Byte
        3. 27.4.2.3  Receive Byte
        4. 27.4.2.4  Write Byte and Write Word
        5. 27.4.2.5  Read Byte and Read Word
        6. 27.4.2.6  Process Call
        7. 27.4.2.7  Block Write
        8. 27.4.2.8  Block Read
        9. 27.4.2.9  Block Write-Block Read Process Call
        10. 27.4.2.10 Alert Response
        11. 27.4.2.11 Extended Command
        12. 27.4.2.12 Group Command
    5. 27.5 PMBus Registers
      1. 27.5.1 PMBUS Base Address Table
      2. 27.5.2 PMBUS_REGS Registers
      3. 27.5.3 PMBUS Registers to Driverlib Functions
  30. 28Controller Area Network (CAN)
    1. 28.1  Introduction
      1. 28.1.1 DCAN Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Block Diagram
        1. 28.1.3.1 CAN Core
        2. 28.1.3.2 Message Handler
        3. 28.1.3.3 Message RAM
        4. 28.1.3.4 Registers and Message Object Access (IFx)
    2. 28.2  Functional Description
      1. 28.2.1 Configuring Device Pins
      2. 28.2.2 Address/Data Bus Bridge
    3. 28.3  Operating Modes
      1. 28.3.1 Initialization
      2. 28.3.2 CAN Message Transfer (Normal Operation)
        1. 28.3.2.1 Disabled Automatic Retransmission
        2. 28.3.2.2 Auto-Bus-On
      3. 28.3.3 Test Modes
        1. 28.3.3.1 Silent Mode
        2. 28.3.3.2 Loopback Mode
        3. 28.3.3.3 External Loopback Mode
        4. 28.3.3.4 Loopback Combined with Silent Mode
    4. 28.4  Multiple Clock Source
    5. 28.5  Interrupt Functionality
      1. 28.5.1 Message Object Interrupts
      2. 28.5.2 Status Change Interrupts
      3. 28.5.3 Error Interrupts
      4. 28.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 28.5.5 Interrupt Topologies
    6. 28.6  DMA Functionality
    7. 28.7  Parity Check Mechanism
      1. 28.7.1 Behavior on Parity Error
    8. 28.8  Debug Mode
    9. 28.9  Module Initialization
    10. 28.10 Configuration of Message Objects
      1. 28.10.1 Configuration of a Transmit Object for Data Frames
      2. 28.10.2 Configuration of a Transmit Object for Remote Frames
      3. 28.10.3 Configuration of a Single Receive Object for Data Frames
      4. 28.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 28.10.5 Configuration of a FIFO Buffer
    11. 28.11 Message Handling
      1. 28.11.1  Message Handler Overview
      2. 28.11.2  Receive/Transmit Priority
      3. 28.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 28.11.4  Updating a Transmit Object
      5. 28.11.5  Changing a Transmit Object
      6. 28.11.6  Acceptance Filtering of Received Messages
      7. 28.11.7  Reception of Data Frames
      8. 28.11.8  Reception of Remote Frames
      9. 28.11.9  Reading Received Messages
      10. 28.11.10 Requesting New Data for a Receive Object
      11. 28.11.11 Storing Received Messages in FIFO Buffers
      12. 28.11.12 Reading from a FIFO Buffer
    12. 28.12 CAN Bit Timing
      1. 28.12.1 Bit Time and Bit Rate
        1. 28.12.1.1 Synchronization Segment
        2. 28.12.1.2 Propagation Time Segment
        3. 28.12.1.3 Phase Buffer Segments and Synchronization
        4. 28.12.1.4 Oscillator Tolerance Range
      2. 28.12.2 Configuration of the CAN Bit Timing
        1. 28.12.2.1 Calculation of the Bit Timing Parameters
        2. 28.12.2.2 Example for Bit Timing at High Baudrate
        3. 28.12.2.3 Example for Bit Timing at Low Baudrate
    13. 28.13 Message Interface Register Sets
      1. 28.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 28.13.2 Message Interface Register Set 3 (IF3)
    14. 28.14 Message RAM
      1. 28.14.1 Structure of Message Objects
      2. 28.14.2 Addressing Message Objects in RAM
      3. 28.14.3 Message RAM Representation in Debug Mode
    15. 28.15 Software
      1. 28.15.1 CAN Examples
        1. 28.15.1.1 CAN External Loopback
        2. 28.15.1.2 CAN External Loopback with Interrupts
        3. 28.15.1.3 CAN External Loopback with DMA
        4. 28.15.1.4 CAN Transmit and Receive Configurations
        5. 28.15.1.5 CAN Error Generation Example
        6. 28.15.1.6 CAN Remote Request Loopback
        7. 28.15.1.7 CAN example that illustrates the usage of Mask registers
    16. 28.16 CAN Registers
      1. 28.16.1 CAN Base Address Table
      2. 28.16.2 CAN_REGS Registers
      3. 28.16.3 CAN Registers to Driverlib Functions
  31. 29Modular Controller Area Network (MCAN)
    1. 29.1 MCAN Introduction
      1. 29.1.1 MCAN Related Collateral
      2. 29.1.2 MCAN Features
    2. 29.2 MCAN Environment
    3. 29.3 CAN Network Basics
    4. 29.4 MCAN Integration
    5. 29.5 MCAN Functional Description
      1. 29.5.1  Module Clocking Requirements
      2. 29.5.2  Interrupt Requests
      3. 29.5.3  Operating Modes
        1. 29.5.3.1 Software Initialization
        2. 29.5.3.2 Normal Operation
        3. 29.5.3.3 CAN FD Operation
      4. 29.5.4  Transmitter Delay Compensation
        1. 29.5.4.1 Description
        2. 29.5.4.2 Transmitter Delay Compensation Measurement
      5. 29.5.5  Restricted Operation Mode
      6. 29.5.6  Bus Monitoring Mode
      7. 29.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 29.5.7.1 Frame Transmission in DAR Mode
      8. 29.5.8  Clock Stop Mode
        1. 29.5.8.1 Suspend Mode
        2. 29.5.8.2 Wakeup Request
      9. 29.5.9  Test Modes
        1. 29.5.9.1 External Loop Back Mode
        2. 29.5.9.2 Internal Loop Back Mode
      10. 29.5.10 Timestamp Generation
        1. 29.5.10.1 External Timestamp Counter
      11. 29.5.11 Timeout Counter
      12. 29.5.12 Safety
        1. 29.5.12.1 ECC Wrapper
        2. 29.5.12.2 ECC Aggregator
          1. 29.5.12.2.1 ECC Aggregator Overview
          2. 29.5.12.2.2 ECC Aggregator Registers
        3. 29.5.12.3 Reads to ECC Control and Status Registers
        4. 29.5.12.4 ECC Interrupts
      13. 29.5.13 Rx Handling
        1. 29.5.13.1 Acceptance Filtering
          1. 29.5.13.1.1 Range Filter
          2. 29.5.13.1.2 Filter for Specific IDs
          3. 29.5.13.1.3 Classic Bit Mask Filter
          4. 29.5.13.1.4 Standard Message ID Filtering
          5. 29.5.13.1.5 Extended Message ID Filtering
        2. 29.5.13.2 Rx FIFOs
          1. 29.5.13.2.1 Rx FIFO Blocking Mode
          2. 29.5.13.2.2 Rx FIFO Overwrite Mode
        3. 29.5.13.3 Dedicated Rx Buffers
          1. 29.5.13.3.1 Rx Buffer Handling
      14. 29.5.14 Tx Handling
        1. 29.5.14.1 Transmit Pause
        2. 29.5.14.2 Dedicated Tx Buffers
        3. 29.5.14.3 Tx FIFO
        4. 29.5.14.4 Tx Queue
        5. 29.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 29.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 29.5.14.7 Transmit Cancellation
        8. 29.5.14.8 Tx Event Handling
      15. 29.5.15 FIFO Acknowledge Handling
      16. 29.5.16 Message RAM
        1. 29.5.16.1 Message RAM Configuration
        2. 29.5.16.2 Rx Buffer and FIFO Element
        3. 29.5.16.3 Tx Buffer Element
        4. 29.5.16.4 Tx Event FIFO Element
        5. 29.5.16.5 Standard Message ID Filter Element
        6. 29.5.16.6 Extended Message ID Filter Element
    6. 29.6 Software
      1. 29.6.1 MCAN Examples
        1. 29.6.1.1  MCAN Internal Loopback with Interrupt
        2. 29.6.1.2  MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
        3. 29.6.1.3  MCAN receive using Rx Buffer
        4. 29.6.1.4  MCAN External Reception (with mask filter) into RX-FIFO1
        5. 29.6.1.5  MCAN Classic frames transmission using Tx Buffer
        6. 29.6.1.6  MCAN External Reception (with RANGE filter) into RX-FIFO1
        7. 29.6.1.7  MCAN External Transmit using Tx Buffer
        8. 29.6.1.8  MCAN receive using Rx Buffer
        9. 29.6.1.9  MCAN Internal Loopback with Interrupt
        10. 29.6.1.10 MCAN External Transmit using Tx Buffer
    7. 29.7 MCAN Registers
      1. 29.7.1 MCAN Base Address Table
      2. 29.7.2 MCANSS_REGS Registers
      3. 29.7.3 MCAN_REGS Registers
      4. 29.7.4 MCAN_ERROR_REGS Registers
      5. 29.7.5 MCAN Registers to Driverlib Functions
  32. 30Local Interconnect Network (LIN)
    1. 30.1 Introduction
      1. 30.1.1 SCI Features
      2. 30.1.2 LIN Features
      3. 30.1.3 LIN Related Collateral
      4. 30.1.4 Block Diagram
    2. 30.2 Serial Communications Interface Module
      1. 30.2.1 SCI Communication Formats
        1. 30.2.1.1 SCI Frame Formats
        2. 30.2.1.2 SCI Asynchronous Timing Mode
        3. 30.2.1.3 SCI Baud Rate
          1. 30.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 30.2.1.4 SCI Multiprocessor Communication Modes
          1. 30.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 30.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 30.2.1.5 SCI Multibuffered Mode
      2. 30.2.2 SCI Interrupts
        1. 30.2.2.1 Transmit Interrupt
        2. 30.2.2.2 Receive Interrupt
        3. 30.2.2.3 WakeUp Interrupt
        4. 30.2.2.4 Error Interrupts
      3. 30.2.3 SCI DMA Interface
        1. 30.2.3.1 Receive DMA Requests
        2. 30.2.3.2 Transmit DMA Requests
      4. 30.2.4 SCI Configurations
        1. 30.2.4.1 Receiving Data
          1. 30.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 30.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 30.2.4.2 Transmitting Data
          1. 30.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 30.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 30.2.5 SCI Low-Power Mode
        1. 30.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 30.3 Local Interconnect Network Module
      1. 30.3.1 LIN Communication Formats
        1. 30.3.1.1  LIN Standards
        2. 30.3.1.2  Message Frame
          1. 30.3.1.2.1 Message Header
          2. 30.3.1.2.2 Response
        3. 30.3.1.3  Synchronizer
        4. 30.3.1.4  Baud Rate
          1. 30.3.1.4.1 Fractional Divider
          2. 30.3.1.4.2 Superfractional Divider
            1. 30.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 30.3.1.5  Header Generation
          1. 30.3.1.5.1 Event Triggered Frame Handling
          2. 30.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 30.3.1.6  Extended Frames Handling
        7. 30.3.1.7  Timeout Control
          1. 30.3.1.7.1 No-Response Error (NRE)
          2. 30.3.1.7.2 Bus Idle Detection
          3. 30.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 30.3.1.8  TXRX Error Detector (TED)
          1. 30.3.1.8.1 Bit Errors
          2. 30.3.1.8.2 Physical Bus Errors
          3. 30.3.1.8.3 ID Parity Errors
          4. 30.3.1.8.4 Checksum Errors
        9. 30.3.1.9  Message Filtering and Validation
        10. 30.3.1.10 Receive Buffers
        11. 30.3.1.11 Transmit Buffers
      2. 30.3.2 LIN Interrupts
      3. 30.3.3 Servicing LIN Interrupts
      4. 30.3.4 LIN DMA Interface
        1. 30.3.4.1 LIN Receive DMA Requests
        2. 30.3.4.2 LIN Transmit DMA Requests
      5. 30.3.5 LIN Configurations
        1. 30.3.5.1 Receiving Data
          1. 30.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 30.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 30.3.5.2 Transmitting Data
          1. 30.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 30.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 30.4 Low-Power Mode
      1. 30.4.1 Entering Sleep Mode
      2. 30.4.2 Wakeup
      3. 30.4.3 Wakeup Timeouts
    5. 30.5 Emulation Mode
    6. 30.6 Software
      1. 30.6.1 LIN Examples
        1. 30.6.1.1 LIN Internal Loopback with Interrupts
        2. 30.6.1.2 LIN SCI Mode Internal Loopback with Interrupts
        3. 30.6.1.3 LIN SCI MODE Internal Loopback with DMA
        4. 30.6.1.4 LIN Internal Loopback without interrupts(polled mode)
        5. 30.6.1.5 LIN Internal Loopback with Interrupts using Sysconfig
        6. 30.6.1.6 LIN Incomplete Header Detection
        7. 30.6.1.7 LIN SCI MODE (Single Buffer) Internal Loopback with DMA
        8. 30.6.1.8 LIN External Loopback without interrupts(polled mode)
    7. 30.7 SCI/LIN Registers
      1. 30.7.1 LIN Base Address Table
      2. 30.7.2 LIN_REGS Registers
      3. 30.7.3 LIN Registers to Driverlib Functions
  33. 31Fast Serial Interface (FSI)
    1. 31.1 Introduction
      1. 31.1.1 FSI Related Collateral
      2. 31.1.2 FSI Features
    2. 31.2 System-level Integration
      1. 31.2.1 CPU Interface
      2. 31.2.2 Signal Description
        1. 31.2.2.1 Configuring Device Pins
      3. 31.2.3 FSI Interrupts
        1. 31.2.3.1 Transmitter Interrupts
        2. 31.2.3.2 Receiver Interrupts
        3. 31.2.3.3 Configuring Interrupts
        4. 31.2.3.4 Handling Interrupts
      4. 31.2.4 CLA Task Triggering
      5. 31.2.5 DMA Interface
      6. 31.2.6 External Frame Trigger Mux
    3. 31.3 FSI Functional Description
      1. 31.3.1  Introduction to Operation
      2. 31.3.2  FSI Transmitter Module
        1. 31.3.2.1 Initialization
        2. 31.3.2.2 FSI_TX Clocking
        3. 31.3.2.3 Transmitting Frames
          1. 31.3.2.3.1 Software Triggered Frames
          2. 31.3.2.3.2 Externally Triggered Frames
          3. 31.3.2.3.3 Ping Frame Generation
            1. 31.3.2.3.3.1 Automatic Ping Frames
            2. 31.3.2.3.3.2 Software Triggered Ping Frame
            3. 31.3.2.3.3.3 Externally Triggered Ping Frame
          4. 31.3.2.3.4 Transmitting Frames with DMA
        4. 31.3.2.4 Transmit Buffer Management
        5. 31.3.2.5 CRC Submodule
        6. 31.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 31.3.2.7 Reset
      3. 31.3.3  FSI Receiver Module
        1. 31.3.3.1  Initialization
        2. 31.3.3.2  FSI_RX Clocking
        3. 31.3.3.3  Receiving Frames
          1. 31.3.3.3.1 Receiving Frames with DMA
        4. 31.3.3.4  Ping Frame Watchdog
        5. 31.3.3.5  Frame Watchdog
        6. 31.3.3.6  Delay Line Control
        7. 31.3.3.7  Buffer Management
        8. 31.3.3.8  CRC Submodule
        9. 31.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 31.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 31.3.3.11 FSI_RX Reset
      4. 31.3.4  Frame Format
        1. 31.3.4.1 FSI Frame Phases
        2. 31.3.4.2 Frame Types
          1. 31.3.4.2.1 Ping Frames
          2. 31.3.4.2.2 Error Frames
          3. 31.3.4.2.3 Data Frames
        3. 31.3.4.3 Multi-Lane Transmission
      5. 31.3.5  Flush Sequence
      6. 31.3.6  Internal Loopback
      7. 31.3.7  CRC Generation
      8. 31.3.8  ECC Module
      9. 31.3.9  Tag Matching
      10. 31.3.10 User Data Filtering (UDATA Matching)
      11. 31.3.11 TDM Configurations
      12. 31.3.12 FSI Trigger Generation
      13. 31.3.13 FSI-SPI Compatibility Mode
        1. 31.3.13.1 Available SPI Modes
          1. 31.3.13.1.1 FSITX as SPI Master, Transmit Only
            1. 31.3.13.1.1.1 Initialization
            2. 31.3.13.1.1.2 Operation
          2. 31.3.13.1.2 FSIRX as SPI Slave, Receive Only
            1. 31.3.13.1.2.1 Initialization
            2. 31.3.13.1.2.2 Operation
          3. 31.3.13.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Master
            1. 31.3.13.1.3.1 Initialization
            2. 31.3.13.1.3.2 Operation
    4. 31.4 FSI Programing Guide
      1. 31.4.1 Establishing the Communication Link
        1. 31.4.1.1 Establishing the Communication Link from the Master Device
        2. 31.4.1.2 Establishing the Communication Link from the Slave Device
      2. 31.4.2 Register Protection
      3. 31.4.3 Emulation Mode
    5. 31.5 Software
      1. 31.5.1 FSI Examples
        1. 31.5.1.1  FSI Loopback:CPU Control
        2. 31.5.1.2  FSI Loopback CLA control
        3. 31.5.1.3  FSI DMA frame transfers:DMA Control
        4. 31.5.1.4  FSI data transfer by external trigger
        5. 31.5.1.5  FSI data transfers upon CPU Timer event
        6. 31.5.1.6  FSI and SPI communication(fsi_ex6_spi_main_tx)
        7. 31.5.1.7  FSI and SPI communication(fsi_ex7_spi_remote_rx)
        8. 31.5.1.8  FSI P2Point Connection:Rx Side
        9. 31.5.1.9  FSI P2Point Connection:Tx Side
        10. 31.5.1.10 FSI daisy chain topology, lead device example
        11. 31.5.1.11 FSI daisy chain topology, node device example
    6. 31.6 FSI Registers
      1. 31.6.1 FSI Base Address Table
      2. 31.6.2 FSI_TX_REGS Registers
      3. 31.6.3 FSI_RX_REGS Registers
      4. 31.6.4 FSI Registers to Driverlib Functions
  34. 32Configurable Logic Block (CLB)
    1. 32.1 Introduction
      1. 32.1.1 CLB Related Collateral
    2. 32.2 Description
      1. 32.2.1 CLB Clock
    3. 32.3 CLB Input/Output Connection
      1. 32.3.1 Overview
      2. 32.3.2 CLB Input Selection
      3. 32.3.3 CLB Output Selection
      4. 32.3.4 CLB Output Signal Multiplexer
    4. 32.4 CLB Tile
      1. 32.4.1 Static Switch Block
      2. 32.4.2 Counter Block
        1. 32.4.2.1 Counter Description
        2. 32.4.2.2 Counter Operation
        3. 32.4.2.3 Serializer Mode
        4. 32.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 32.4.3 FSM Block
      4. 32.4.4 LUT4 Block
      5. 32.4.5 Output LUT Block
      6. 32.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 32.4.7 High Level Controller (HLC)
        1. 32.4.7.1 High Level Controller Events
        2. 32.4.7.2 High Level Controller Instructions
        3. 32.4.7.3 <Src> and <Dest>
        4. 32.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 32.5 CPU Interface
      1. 32.5.1 Register Description
      2. 32.5.2 Non-Memory Mapped Registers
    6. 32.6 DMA Access
    7. 32.7 CLB Data Export Through SPI RX Buffer
    8. 32.8 Software
      1. 32.8.1 CLB Examples
        1. 32.8.1.1  CLB Empty Project
        2. 32.8.1.2  CLB Combinational Logic
        3. 32.8.1.3  CLB GPIO Input Filter
        4. 32.8.1.4  CLB Auxilary PWM
        5. 32.8.1.5  CLB PWM Protection
        6. 32.8.1.6  CLB Event Window
        7. 32.8.1.7  CLB Signal Generator
        8. 32.8.1.8  CLB State Machine
        9. 32.8.1.9  CLB External Signal AND Gate
        10. 32.8.1.10 CLB Timer
        11. 32.8.1.11 CLB Timer Two States
        12. 32.8.1.12 CLB Interrupt Tag
        13. 32.8.1.13 CLB Output Intersect
        14. 32.8.1.14 CLB PUSH PULL
        15. 32.8.1.15 CLB Multi Tile
        16. 32.8.1.16 CLB Glue Logic
        17. 32.8.1.17 CLB based One-shot PWM
        18. 32.8.1.18 CLB AOC Control
        19. 32.8.1.19 CLB AOC Release Control
        20. 32.8.1.20 CLB XBARs
        21. 32.8.1.21 CLB AOC Control
        22. 32.8.1.22 CLB Serializer
        23. 32.8.1.23 CLB LFSR
        24. 32.8.1.24 CLB Lock Output Mask
        25. 32.8.1.25 CLB INPUT Pipeline Mode
        26. 32.8.1.26 CLB Clocking and PIPELINE Mode
        27. 32.8.1.27 CLB SPI Data Export
        28. 32.8.1.28 CLB SPI Data Export DMA
        29. 32.8.1.29 CLB Trip Zone Timestamp
        30. 32.8.1.30 CLB CRC
        31. 32.8.1.31 CLB TDM Serial Port
        32. 32.8.1.32 CLB LED Driver
    9. 32.9 CLB Registers
      1. 32.9.1 CLB Base Address Table
      2. 32.9.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 32.9.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 32.9.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 32.9.5 CLB Registers to Driverlib Functions
  35. 33Advanced Encryption Standard (AES) Accelerator
    1. 33.1 Introduction
      1. 33.1.1 AES Block Diagram
        1. 33.1.1.1 Interfaces
        2. 33.1.1.2 AES Subsystem
        3. 33.1.1.3 AES Wide-Bus Engine
      2. 33.1.2 AES Algorithm
    2. 33.2 AES Operating Modes
      1. 33.2.1  GCM Operation
      2. 33.2.2  CCM Operation
      3. 33.2.3  XTS Operation
      4. 33.2.4  ECB Feedback Mode
      5. 33.2.5  CBC Feedback Mode
      6. 33.2.6  CTR and ICM Feedback Modes
      7. 33.2.7  CFB Mode
      8. 33.2.8  F8 Mode
      9. 33.2.9  F9 Operation
      10. 33.2.10 CBC-MAC Operation
    3. 33.3 Extended and Combined Modes of Operations
      1. 33.3.1 GCM Protocol Operation
      2. 33.3.2 CCM Protocol Operation
      3. 33.3.3 Hardware Requests
    4. 33.4 AES Module Programming Guide
      1. 33.4.1 AES Low-Level Programming Models
        1. 33.4.1.1 Global Initialization
        2. 33.4.1.2 AES Operating Modes Configuration
        3. 33.4.1.3 AES Mode Configurations
        4. 33.4.1.4 AES Events Servicing
    5. 33.5 Software
      1. 33.5.1 AES Examples
        1. 33.5.1.1 AES ECB Encryption Example
        2. 33.5.1.2 AES ECB De-cryption Example
        3. 33.5.1.3 AES GCM Encryption Example
        4. 33.5.1.4 AES GCM Decryption Example
    6. 33.6 AES Registers
      1. 33.6.1 AES Base Address Table
      2. 33.6.2 AES_REGS Registers
      3. 33.6.3 AES_SS_REGS Registers
      4. 33.6.4 Register to Driverlib Function Mapping
        1. 33.6.4.1 AES Registers to Driverlib Functions
        2. 33.6.4.2 AES_SS Registers to Driverlib Functions
  36. 34Embedded Pattern Generator (EPG)
    1. 34.1 Introduction
      1. 34.1.1 Features
      2. 34.1.2 EPG Block Diagram
      3. 34.1.3 EPG Related Collateral
    2. 34.2 Clock Generator Modules
      1. 34.2.1 DCLK (50% duty cycle clock)
      2. 34.2.2 Clock Stop
    3. 34.3 Signal Generator Module
    4. 34.4 EPG Peripheral Signal Mux Selection
    5. 34.5 EPG Example Use Cases
      1. 34.5.1 EPG Example: Synchronous Clocks with Offset
        1. 34.5.1.1 Synchronous Clocks with Offset Register Configuration
      2. 34.5.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 34.5.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 34.5.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 34.5.3.1 Serial Data Bit Stream (MSB first) Register Configuration
    6. 34.6 EPG Interrupt
    7. 34.7 Software
      1. 34.7.1 EPG Examples
        1. 34.7.1.1 EPG Generating Synchronous Clocks
        2. 34.7.1.2 EPG Generating Two Offset Clocks
        3. 34.7.1.3 EPG Generating Two Offset Clocks With SIGGEN
        4. 34.7.1.4 EPG Generate Serial Data
        5. 34.7.1.5 EPG Generate Serial Data Shift Mode
    8. 34.8 EPG Registers
      1. 34.8.1 EPG Base Address Table
      2. 34.8.2 EPG_REGS Registers
      3. 34.8.3 EPG_MUX_REGS Registers
      4. 34.8.4 EPG Registers to Driverlib Functions
  37. 35Revision History

28.16.2 CAN_REGS Registers

Table 28-8 lists the memory-mapped registers for the CAN_REGS registers. All register offset addresses not listed in Table 28-8 should be considered as reserved locations and the register contents should not be modified.

Table 28-8 CAN_REGS Registers
Offset (x8) Offset (x16)Acronym Register Name Write Protection Section
0h0hCAN_CTLCAN Control RegisterGo
8h4hCAN_ESError and Status RegisterGo
10h8hCAN_ERRCError Counter RegisterGo
18hChCAN_BTRBit Timing RegisterGo
20h10hCAN_INTInterrupt RegisterGo
28h14hCAN_TESTTest RegisterGo
38h1ChCAN_PERRCAN Parity Error Code RegisterGo
80h40hCAN_RAM_INITCAN RAM Initialization RegisterGo
A0h50hCAN_GLB_INT_ENCAN Global Interrupt Enable RegisterGo
A8h54hCAN_GLB_INT_FLGCAN Global Interrupt Flag RegisterGo
B0h58hCAN_GLB_INT_CLRCAN Global Interrupt Clear RegisterGo
100h80hCAN_ABOTRAuto-Bus-On Time RegisterGo
108h84hCAN_TXRQ_XCAN Transmission Request RegisterGo
110h88hCAN_TXRQ_21CAN Transmission Request 2_1 RegisterGo
130h98hCAN_NDAT_XCAN New Data RegisterGo
138h9ChCAN_NDAT_21CAN New Data 2_1 RegisterGo
158hAChCAN_IPEN_XCAN Interrupt Pending RegisterGo
160hB0hCAN_IPEN_21CAN Interrupt Pending 2_1 RegisterGo
180hC0hCAN_MVAL_XCAN Message Valid RegisterGo
188hC4hCAN_MVAL_21CAN Message Valid 2_1 RegisterGo
1B0hD8hCAN_IP_MUX21CAN Interrupt Multiplexer 2_1 RegisterGo
200h100hCAN_IF1CMDIF1 Command RegisterGo
208h104hCAN_IF1MSKIF1 Mask RegisterGo
210h108hCAN_IF1ARBIF1 Arbitration RegisterGo
218h10ChCAN_IF1MCTLIF1 Message Control RegisterGo
220h110hCAN_IF1DATAIF1 Data A RegisterGo
228h114hCAN_IF1DATBIF1 Data B RegisterGo
240h120hCAN_IF2CMDIF2 Command RegisterGo
248h124hCAN_IF2MSKIF2 Mask RegisterGo
250h128hCAN_IF2ARBIF2 Arbitration RegisterGo
258h12ChCAN_IF2MCTLIF2 Message Control RegisterGo
260h130hCAN_IF2DATAIF2 Data A RegisterGo
268h134hCAN_IF2DATBIF2 Data B RegisterGo
280h140hCAN_IF3OBSIF3 Observation RegisterGo
288h144hCAN_IF3MSKIF3 Mask RegisterGo
290h148hCAN_IF3ARBIF3 Arbitration RegisterGo
298h14ChCAN_IF3MCTLIF3 Message Control RegisterGo
2A0h150hCAN_IF3DATAIF3 Data A RegisterGo
2A8h154hCAN_IF3DATBIF3 Data B RegisterGo
2C0h160hCAN_IF3UPDIF3 Update Enable RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 28-9 shows the codes that are used for access types in this section.

Table 28-9 CAN_REGS Access Type Codes
Access Type Code Description
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

28.16.2.1 CAN_CTL Register (Offset (x8) = 0h, Offset (x16) = 0h) [Reset = 00001401h]

CAN_CTL is shown in Figure 28-22 and described in Table 28-10.

Return to the Summary Table.

This register is used for configuring the CAN module in terms of interrupts, parity, debug-mode behavior etc.

Figure 28-22 CAN_CTL Register
3130292827262524
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDE3DE2DE1IE1INITDBG
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
15141312111098
SWRRESERVEDPMDABOIDS
R-0/W1C-0hR-0hR/W-5hR/W-0hR/W-0h
76543210
TestCCEDARRESERVEDEIESIEIE0Init
R/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 28-10 CAN_CTL Register Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23-21 RESERVED R 0h Reserved
20 DE3 R/W 0h Enable DMA request line for IF3

0 Disabled

1 Enabled

Note: A pending DMA request for IF3 remains active until first access to one of the IF3 registers.

Reset type: SYSRSn
19 DE2 R/W 0h Enable DMA request line for IF2

0 Disabled

1 Enabled

Note: A pending DMA request for IF1 remains active until first access to one of the IF2 registers.

Reset type: SYSRSn
18 DE1 R/W 0h Enable DMA request line for IF1

0 Disabled

1 Enabled

Note: A pending DMA request for IF1 remains active until first access to one of the IF1 registers.

Reset type: SYSRSn
17 IE1 R/W 0h Interrupt line 1 Enable

0 CANINT1 is disabled.

1 CANINT1 is enabled. Interrupts will assert CANINT1 line to 1
line remains active until pending interrupts are processed.

Reset type: SYSRSn
16 INITDBG R 0h Debug Mode Status Bit: This bit indicates the internal init state for a debug access

0 Not in debug mode, or debug mode requested but not entered.

1 Debug mode requested and internally entered
the CAN module is ready for debug accesses.

Reset type: SYSRSn
15 SWR R-0/W1C 0h Software Reset Enable Bit: This bit activates the software reset.

0 Normal Operation.

1 Module is forced to reset state. This bit will get cleared automatically one clock cycle after execution of software reset.

Note: To execute software reset, the following procedure is necessary:
1. Set INIT bit to shut down CAN communication.
2. Set SWR bit.

Note: This bit is write-protected by Init bit. If module is reset using the SWR bit, no user configuration is lost. Only status bits get reset along with logic which needs to be reset for the next CAN transaction. If module is reset using SOFTPRES register, entire module will get reset, including configuration registers.

Reset type: SYSRSn
14 RESERVED R 0h Reserved
13-10 PMD R/W 5h Parity on/off

0101 Parity function disabled

Any other value - Parity function enabled

Reset type: SYSRSn
9 ABO R/W 0h Auto-Bus-On Enable

0 The Auto-Bus-On feature is disabled

1 The Auto-Bus-On feature is enabled

Reset type: SYSRSn
8 IDS R/W 0h Interruption Debug Support Enable

0 When Debug mode is requested, the CAN module will wait for a started transmission or reception to be completed before entering Debug mode

1 When Debug mode is requested, the CAN module will interrupt any transmission or reception, and enter Debug mode immediately.

Reset type: SYSRSn
7 Test R/W 0h Test Mode Enable

0 Disable Test Mode (Normal operation)

1 Enable Test Mode

Reset type: SYSRSn
6 CCE R/W 0h Configuration Change Enable

0 The CPU has no write access to the configuration registers.

1 The CPU has write access to the configuration registers (when Init bit is set).

Reset type: SYSRSn
5 DAR R/W 0h Disable Automatic Retransmission

0 Automatic Retransmission of 'not successful' messages enabled.

1 Automatic Retransmission disabled.

Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 EIE R/W 0h Error Interrupt Enable

0 Disabled - PER, BOff and EWarn bits cannot generate an interrupt.

1 Enabled - PER, BOff and EWarn bits can generate an interrupt at CANINT0 line and affect the Interrupt Register.

Reset type: SYSRSn
2 SIE R/W 0h Status Change Interrupt Enable

0 Disabled - RxOk, TxOk and LEC bits cannot generate an interrupt.

1 Enabled - RxOk, TxOk and LEC can generate an interrupt on the CANINT0 line

Reset type: SYSRSn
1 IE0 R/W 0h Interrupt line 0 Enable

0 CANINT0 is disabled.

1 CANINT0 is enabled. Interrupts will assert CANINT0 line to 1
line remains active until pending interrupts are processed.

Reset type: SYSRSn
0 Init R/W 1h Initialization Mode

This bit is used to keep the CAN module inactive during bit timing configuration and message RAM initialization. It is set automatically during a bus off event. Clearing this bit will not shorten the bus recovery time.

0 CAN module processes messages normally

1 CAN module ignores bus activity

Reset type: SYSRSn

28.16.2.2 CAN_ES Register (Offset (x8) = 8h, Offset (x16) = 4h) [Reset = 00000007h]

CAN_ES is shown in Figure 28-23 and described in Table 28-11.

Return to the Summary Table.

This register indicates error conditions, if any, of the CAN module. Interrupts are generated by PER, BOff and EWarn bits (if EIE bit in CAN Control Register is set) and by RxOk, TxOk, and LEC bits (if SIE bit in CAN Control Register is set). A change of bit EPass will not generate an Interrupt.

Reading the Error and Status Register clears the PER, RxOk and TxOk bits and sets the LEC to value '7'. Additionally, the Status Interrupt value (0x8000) in the Interrupt Register will be replaced by the next lower priority interrupt value.

For debug support, the auto clear functionality of Error and Status Register (clear of status flags by read) is disabled when in Debug/Suspend mode.

Figure 28-23 CAN_ES Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDPER
R-0hR-0hR-0hR-0h
76543210
BOffEWarnEPassRxOkTxOkLEC
R-0hR-0hR-0hR-0hR-0hR-7h
Table 28-11 CAN_ES Register Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 PER R 0h Parity Error Detected: This bit will be reset after the CPU reads the register.

0 No parity error has been detected since last read access.

1 The parity check mechanism has detected a parity error in the Message RAM.

Reset type: SYSRSn
7 BOff R 0h Bus-off Status Bit:

0 The CAN module is not in Bus-Off state.

1 The CAN module is in Bus-Off state.

Reset type: SYSRSn
6 EWarn R 0h Warning State Bit:

0 Both error counters are below the error warning limit of 96.

1 At least one of the error counters has reached the error warning limit of 96.

Reset type: SYSRSn
5 EPass R 0h Error Passive State

0 On CAN Bus error, the CAN could send active error frames.

1 The CAN Core is in the error passive state as defined in the CAN Specification.

Reset type: SYSRSn
4 RxOk R 0h Reception status Bit: This bit indicates the status of reception. The bit will be reset after the CPU reads the register.

0 No message has been successfully received since the last time when this bit was read by the CPU. This bit is never reset by CAN internal events.

1 A message has been successfully received since the last time when this bit was reset by a read access of the CPU. This bit will be set independent of the result of acceptance filtering.

Reset type: SYSRSn
3 TxOk R 0h Transmission status Bit: This bit indicates the status of transmission. The bit will be reset after the CPU reads the register.

0 No message has been successfully transmitted since the last time when this bit was read by the CPU. This bit is never reset by CAN internal events.

1 A message has been successfully transmitted (error free and acknowledged by at least one other node) since the last time when this bit was cleared by a read access of the CPU.

Reset type: SYSRSn
2-0 LEC R 7h Last Error Code

The LEC field indicates the type of the last error on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. This field will be reset to '7' whenever the CPU reads the register.

0 No Error

1 Stuff Error: More than five equal bits in a row have been detected in a part of a received message where this is not allowed.

2 Form Error: A fixed format part of a received frame has the wrong format.

3 Ack Error: The message this CAN Core transmitted was not acknowledged by another node.

4 Bit1 Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.

5 Bit0 Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (logical value '0'), but the monitored bus level was recessive. During Bus-Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus-Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

6 CRC Error: In a received message, the CRC check sum was incorrect. (CRC received for an incoming message does not match the calculated CRC for the received data).

7 No CAN bus event was detected since the last time when CPU has read the Error and Status Register. Any read access to the Error and Status Register re-initializes the LEC to value '7'.

Reset type: SYSRSn

28.16.2.3 CAN_ERRC Register (Offset (x8) = 10h, Offset (x16) = 8h) [Reset = 00000000h]

CAN_ERRC is shown in Figure 28-24 and described in Table 28-12.

Return to the Summary Table.

This register reflects the value of the Transmit and Receive error counters

Figure 28-24 CAN_ERRC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RPRECTEC
R-0hR-0hR-0h
Table 28-12 CAN_ERRC Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RP R 0h Receive Error Passive

0 The Receive Error Counter is below the error passive level.

1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification.

Reset type: SYSRSn
14-8 REC R 0h Receive Error Counter

Actual state of the Receive Error Counter (values from 0 to 127).

Reset type: SYSRSn
7-0 TEC R 0h Transmit Error Counter

Actual state of the Transmit Error Counter. (values from 0 to 255).

Reset type: SYSRSn

28.16.2.4 CAN_BTR Register (Offset (x8) = 18h, Offset (x16) = Ch) [Reset = 00002301h]

CAN_BTR is shown in Figure 28-25 and described in Table 28-13.

Return to the Summary Table.

This register is used to configure the bit-timing parameters for the CAN module. This register is only writable if CCE and Init bits in the CAN Control Register are set.

The CAN bit time may be programmed in the range of 8 to 25 time quanta.

The CAN time quantum may be programmed in the range of 1 to1024 CAN_CLK periods.

Figure 28-25 CAN_BTR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBRPE
R-0hR/W-0h
15141312111098
RESERVEDTSEG2TSEG1
R-0hR/W-2hR/W-3h
76543210
SJWBRP
R/W-0hR/W-1h
Table 28-13 CAN_BTR Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-16 BRPE R/W 0h Baud Rate Prescaler Extension

Valid programmed values are 0 to 15.

By programming BRPE the Baud Rate Prescaler can be extended to values up to 1024.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn
15 RESERVED R 0h Reserved
14-12 TSEG2 R/W 2h Time segment after the sample point Valid programmed values are 0 to 7.

The actual TSeg2 value which is interpreted for the Bit Timing will be the programmed TSeg2 value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn
11-8 TSEG1 R/W 3h Time segment before the sample point Valid programmed values are 1 to 15.

The actual TSeg1 value interpreted for the Bit Timing will be the programmed TSeg1 value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn
7-6 SJW R/W 0h Synchronization Jump Width Valid programmed values are 0 to 3.

The actual SJW value interpreted for the Synchronization will be the programmed SJW value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn
5-0 BRP R/W 1h Baud Rate Prescaler-

Value by which the CAN_CLK frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta.

Valid programmed values are 0 to 63.

The actual BRP value interpreted for the Bit Timing will be the programmed BRP value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn

28.16.2.5 CAN_INT Register (Offset (x8) = 20h, Offset (x16) = 10h) [Reset = 00000000h]

CAN_INT is shown in Figure 28-26 and described in Table 28-14.

Return to the Summary Table.

This register is used to identify the source of the interrupt(s).

Figure 28-26 CAN_INT Register
313029282726252423222120191817161514131211109876543210
RESERVEDINT1IDINT0ID
R-0hR-0hR-0h
Table 28-14 CAN_INT Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-16 INT1ID R 0h Interrupt 1 Cause

0x00 No interrupt is pending.

0x01-0x20 Number of message object (mailbox) which caused the interrupt.

0x21-0xFF Unused.

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority.

Note: The CANINT1 interrupt line remains active until INT1ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. A message interrupt is cleared by clearing the mailbox's IntPnd bit. Among the message interrupts, the mailbox's interrupt priority decreases with increasing message number.

Reset type: SYSRSn
15-0 INT0ID R 0h Interrupt 0 Cause

0x0000 - No interrupt is pending.

0x0001 - 0x0020 - Number of message object which caused the interrupt.

0x0021 - 0x7FFF - Unused.

0x8000 - Error and Status Register value is not 0x07.

0x8001 - 0xFFFF - Unused.

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority.

Note: The CANINT0 interrupt line remains active until INT0ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. The Status Interrupt has the highest priority. Among the message interrupts, the message object's interrupt priority decreases with increasing message number.

Reset type: SYSRSn

28.16.2.6 CAN_TEST Register (Offset (x8) = 28h, Offset (x16) = 14h) [Reset = 00000000h]

CAN_TEST is shown in Figure 28-27 and described in Table 28-15.

Return to the Summary Table.

This register is used to configure the various test options supported. For all test modes, the Test bit in CAN Control Register needs to be set to one. If Test bit is set, the RDA, EXL, Tx1, Tx0, LBack and Silent bits are writable. Bit Rx monitors the state of CANRX pin and therefore is only readable. All Test Register functions are disabled when Test bit is cleared.

Note: Setting Tx[1:0] other than '00' will disturb message transfer.

Note: When the internal loop back mode is active (bit LBack is set), bit EXL will be ignored.

Figure 28-27 CAN_TEST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRDAEXL
R-0hR/W-0hR/W-0h
76543210
RXTXLBACKSILENTRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 28-15 CAN_TEST Register Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 RDA R/W 0h RAM Direct Access Enable:

0 Normal Operation.

1 Direct access to the RAM is enabled while in Test Mode.

Reset type: SYSRSn
8 EXL R/W 0h External Loop Back Mode:

0 Disabled.

1 Enabled.

Reset type: SYSRSn
7 RX R 0h Monitors the actual value of the CANRX pin:

0 The CAN bus is dominant.

1 The CAN bus is recessive.

Reset type: SYSRSn
6-5 TX R/W 0h Control of CANTX pin:

00 Normal operation, CANTX is controlled by the CAN Core.

01 Sample Point can be monitored at CANTX pin.

10 CANTX pin drives a dominant value.

11 CANTX pin drives a recessive value.

Reset type: SYSRSn
4 LBACK R/W 0h Loop Back Mode:

0 Disabled.

1 Enabled.

Reset type: SYSRSn
3 SILENT R/W 0h Silent Mode:

0 Disabled.

1 Enabled.

Reset type: SYSRSn
2-0 RESERVED R 0h Reserved

28.16.2.7 CAN_PERR Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [Reset = 00000XXXh]

CAN_PERR is shown in Figure 28-28 and described in Table 28-16.

Return to the Summary Table.

This register indicates the Word/Mailbox number where a parity error has been detected. If a parity error is detected, the PER flag will be set in the Error and Status Register. This bit is not reset by the parity check mechanism
it must be reset by reading the Error and Status Register. In addition to the PER flag, the Parity Error Code Register will indicate the memory area where the parity error has been detected. If more than one word with a parity error was detected, the highest word number with a parity error will be displayed. After a parity error has been detected, the register will hold the last error code until power is removed.

Figure 28-28 CAN_PERR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDWORD_NUMMSG_NUM
R-0hR-XR-X
Table 28-16 CAN_PERR Register Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h Reserved
10-8 WORD_NUM R X 0x01-0x05 Word number where parity error has been detected.
RDA word number (1 to 5) of the mailbox (according to the
Message RAM representation in RDA mode).

Reset type: SYSRSn
7-0 MSG_NUM R X 0x01-0x21 Mailbox number where parity error has been detected

Reset type: SYSRSn

28.16.2.8 CAN_RAM_INIT Register (Offset (x8) = 80h, Offset (x16) = 40h) [Reset = 00000005h]

CAN_RAM_INIT is shown in Figure 28-29 and described in Table 28-17.

Return to the Summary Table.

This register is used to initialize the Mailbox RAM. It clears the entire mailbox RAM, including the MsgVal bits.

Figure 28-29 CAN_RAM_INIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRAM_INIT_DONECAN_RAM_INITKEY3KEY2KEY1KEY0
R-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-1h
Table 28-17 CAN_RAM_INIT Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 RAM_INIT_DONE R 0h CAN Mailbox RAM initialization status:

0 Read: Initialization is on-going or initialization not initiated.

1 Read: Initialization complete

Reset type: SYSRSn
4 CAN_RAM_INIT R/W 0h Initiate CAN Mailbox RAM initialization:

0 Read: Initialization complete or initialization not initiated.
Write: No action
1 Read: Initialization is on-going
Write: Initiate CAN Mailbox RAM initialization. After initialization, this bit will be automatically cleared to 0.

Reset type: SYSRSn
3 KEY3 R/W 0h See Key 0

Reset type: SYSRSn
2 KEY2 R/W 1h See Key 0

Reset type: SYSRSn
1 KEY1 R/W 0h See Key 0

Reset type: SYSRSn
0 KEY0 R/W 1h KEY3-KEY0 should be 1010 for any write to this register to be valid. These bits will be restored to their reset state after the CAN RAM initialization is complete.

Reset type: SYSRSn

28.16.2.9 CAN_GLB_INT_EN Register (Offset (x8) = A0h, Offset (x16) = 50h) [Reset = 00000000h]

CAN_GLB_INT_EN is shown in Figure 28-30 and described in Table 28-18.

Return to the Summary Table.

This register is used to enable the interrupt lines to the PIE.

Figure 28-30 CAN_GLB_INT_EN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDGLBINT1_ENGLBINT0_EN
R-0hR/W-0hR/W-0h
Table 28-18 CAN_GLB_INT_EN Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 GLBINT1_EN R/W 0h Global Interrupt Enable for CANINT1

0 CANINT1 does not generate interrupt to PIE

1 CANINT1 generates interrupt to PIE if interrupt condition occurs

Reset type: SYSRSn
0 GLBINT0_EN R/W 0h Global Interrupt Enable for CANINT0

0 CANINT0 does not generate interrupt to PIE

1 CANINT0 generates interrupt to PIE if interrupt condition occurs

Reset type: SYSRSn

28.16.2.10 CAN_GLB_INT_FLG Register (Offset (x8) = A8h, Offset (x16) = 54h) [Reset = 00000000h]

CAN_GLB_INT_FLG is shown in Figure 28-31 and described in Table 28-19.

Return to the Summary Table.

This register indicates if and when the interrupt line to the PIE is active.

Figure 28-31 CAN_GLB_INT_FLG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT1_FLGINT0_FLG
R-0hR-0hR-0h
Table 28-19 CAN_GLB_INT_FLG Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 INT1_FLG R 0h CANINT1 Flag

0 No interrupt generated

1 Interrupt is generated due to CANINT1 (refer to CAN Interrupt Status Register for the condition)

Reset type: SYSRSn
0 INT0_FLG R 0h CANINT0 Flag

0 No interrupt generated

1 Interrupt is generated due to CANINT0 (refer to CAN Interrupt Status Register for the condition)

Reset type: SYSRSn

28.16.2.11 CAN_GLB_INT_CLR Register (Offset (x8) = B0h, Offset (x16) = 58h) [Reset = 00000000h]

CAN_GLB_INT_CLR is shown in Figure 28-32 and described in Table 28-20.

Return to the Summary Table.

This register is used to clear the interrupt to the PIE.

Figure 28-32 CAN_GLB_INT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT1_FLG_CLRINT0_FLG_CLR
R-0hW-0hW-0h
Table 28-20 CAN_GLB_INT_CLR Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 INT1_FLG_CLR W 0h Global Interrupt flag clear for CANINT1

0 No effect

1 Write 1 to clear the corresponding bit of the Global Interrupt Flag Register and allow the PIE to receive another interrupt from CANINT1.

Reset type: SYSRSn
0 INT0_FLG_CLR W 0h Global Interrupt flag clear for CANINT0

0 No effect

1 Write 1 to clear the corresponding bit of the Global Interrupt Flag Register and allow the PIE to receive another interrupt from CANINT0.

Reset type: SYSRSn

28.16.2.12 CAN_ABOTR Register (Offset (x8) = 100h, Offset (x16) = 80h) [Reset = 00000000h]

CAN_ABOTR is shown in Figure 28-33 and described in Table 28-21.

Return to the Summary Table.

This register is used to introduce a variable delay before the Bus-off recovery sequence is started.

Figure 28-33 CAN_ABOTR Register
313029282726252423222120191817161514131211109876543210
ABO_Time
R/W-0h
Table 28-21 CAN_ABOTR Register Field Descriptions
Bit Field Type Reset Description
31-0 ABO_Time R/W 0h Auto-Bus-On Timer

Number of clock cycles before a Bus-Off recovery sequence is started by clearing the Init bit. 'Clock' refers to the input clock to the CAN module. This function has to be enabled by setting bit ABO in CAN Control Register.

The Auto-Bus-On timer is realized by a 32-bit counter which starts to count down to zero when the module goes Bus-Off. The counter will be reloaded with the preload value of the ABO Time register after this phase.

NOTE: On write access to the CAN Control register while Auto-Bus-On timer is running, the Auto-Bus-On procedure will be aborted.

NOTE: During Debug mode, running Auto-Bus-On timer will be paused.

Reset type: SYSRSn

28.16.2.13 CAN_TXRQ_X Register (Offset (x8) = 108h, Offset (x16) = 84h) [Reset = 00000000h]

CAN_TXRQ_X is shown in Figure 28-34 and described in Table 28-22.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN Transmission Request 21 Register (CAN_TXRQ_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the TxRqst bits of these message objects is set, the corresponding bit in this register will be set.

Figure 28-34 CAN_TXRQ_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTxRqstReg2TxRqstReg1
R-0hR-0hR-0h
Table 28-22 CAN_TXRQ_X Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3-2 TxRqstReg2 R 0h Transmit Request Register 2 flag:

Bit 2 represents byte 2 of CAN_TXRQ_21. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_TXRQ_21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn
1-0 TxRqstReg1 R 0h Transmit Request Register 1 flag:

Bit 0 represents byte 0 of CAN_TXRQ_21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_TXRQ_21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

28.16.2.14 CAN_TXRQ_21 Register (Offset (x8) = 110h, Offset (x16) = 88h) [Reset = 00000000h]

CAN_TXRQ_21 is shown in Figure 28-35 and described in Table 28-23.

Return to the Summary Table.

This register holds the TxRqst bits of the mailboxes. By reading out these bits, the CPU can check for pending transmission requests. The TxRqst bit in a specific mailbox can be set/reset by the CPU via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission.

Figure 28-35 CAN_TXRQ_21 Register
313029282726252423222120191817161514131211109876543210
TxRqst
R-0h
Table 28-23 CAN_TXRQ_21 Register Field Descriptions
Bit Field Type Reset Description
31-0 TxRqst R 0h Transmission Request Bits (for all message objects)

0 No transmission has been requested for this message object.

1 The transmission of this message object is requested and is not yet done.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

28.16.2.15 CAN_NDAT_X Register (Offset (x8) = 130h, Offset (x16) = 98h) [Reset = 00000000h]

CAN_NDAT_X is shown in Figure 28-36 and described in Table 28-24.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN New Data 21 Register (CAN_NDAT _21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the NewDat bits of these mailboxes are set, the corresponding bit in this register will be set.

Figure 28-36 CAN_NDAT_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDNewDatReg2NewDatReg1
R-0hR-0hR-0h
Table 28-24 CAN_NDAT_X Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3-2 NewDatReg2 R 0h New Data Register 2 flag:

Bit 2 represents byte 2 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn
1-0 NewDatReg1 R 0h New Data Register 1 flag:

Bit 0 represents byte 0 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

28.16.2.16 CAN_NDAT_21 Register (Offset (x8) = 138h, Offset (x16) = 9Ch) [Reset = 00000000h]

CAN_NDAT_21 is shown in Figure 28-37 and described in Table 28-25.

Return to the Summary Table.

This register holds the NewDat bits of all mailboxes. By reading out the NewDat bits, the CPU can check for which mailboxes the data portion was updated. The NewDat bit of a specific mailbox can be set/reset by the CPU via the IFx 'Message Interface' Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.

Figure 28-37 CAN_NDAT_21 Register
313029282726252423222120191817161514131211109876543210
NewDat
R-0h
Table 28-25 CAN_NDAT_21 Register Field Descriptions
Bit Field Type Reset Description
31-0 NewDat R 0h New Data Bits (for all message objects)

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

28.16.2.17 CAN_IPEN_X Register (Offset (x8) = 158h, Offset (x16) = ACh) [Reset = 00000000h]

CAN_IPEN_X is shown in Figure 28-38 and described in Table 28-26.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN Interrupt Pending 21 Register (CAN_IPEN_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the IntPnd bits of these mailboxes are set, the corresponding bit in this register will be set.

Figure 28-38 CAN_IPEN_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDIntPndReg2IntPndReg1
R-0hR-0hR-0h
Table 28-26 CAN_IPEN_X Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3-2 IntPndReg2 R 0h Interrupt Pending Register 2 flag:

Bit 2 represents byte 2 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn
1-0 IntPndReg1 R 0h Interrupt Pending Register 1 flag:

Bit 0 represents byte 0 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

28.16.2.18 CAN_IPEN_21 Register (Offset (x8) = 160h, Offset (x16) = B0h) [Reset = 00000000h]

CAN_IPEN_21 is shown in Figure 28-39 and described in Table 28-27.

Return to the Summary Table.

This register holds the IntPnd bits of the mailboxes. By reading out these bits, the CPU can check for pending interrupts in the mailboxes. The IntPnd bit of a specific mailbox can be set/reset by the CPU via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission.

Figure 28-39 CAN_IPEN_21 Register
313029282726252423222120191817161514131211109876543210
IntPnd
R-0h
Table 28-27 CAN_IPEN_21 Register Field Descriptions
Bit Field Type Reset Description
31-0 IntPnd R 0h Interrupt Pending bits: This register contains the bits that indicate the pending interrupts in each one of the 32 mailboxes.

0 This mailbox is not the source of an interrupt.

1 This mailbox is the source of an interrupt.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

28.16.2.19 CAN_MVAL_X Register (Offset (x8) = 180h, Offset (x16) = C0h) [Reset = 00000000h]

CAN_MVAL_X is shown in Figure 28-40 and described in Table 28-28.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN Message Valid 2_1 Register (CAN_MVAL_21) is set.Each bit in this register represents a group of eight mailboxes. If at least one of the MsgVal bits of these mailboxes are set, the corresponding bit in this register will be set.

Figure 28-40 CAN_MVAL_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMsgValReg2MsgValReg1
R-0hR-0hR-0h
Table 28-28 CAN_MVAL_X Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3-2 MsgValReg2 R 0h Message Valid Register 2 flag:

Bit 2 represents byte 2 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn
1-0 MsgValReg1 R 0h Message Valid Register 1 flag:

Bit 0 represents byte 0 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

28.16.2.20 CAN_MVAL_21 Register (Offset (x8) = 188h, Offset (x16) = C4h) [Reset = 00000000h]

CAN_MVAL_21 is shown in Figure 28-41 and described in Table 28-29.

Return to the Summary Table.

This registers hold the MsgVal bits of all mailboxes. By reading out the MsgVal bits, the CPU can check which mailbox is valid. The MsgVal bit of a specific mailbox can be set/reset by the CPU via the IF1/2 'Message Interface' Registers.

Figure 28-41 CAN_MVAL_21 Register
313029282726252423222120191817161514131211109876543210
MsgValReg
R-0h
Table 28-29 CAN_MVAL_21 Register Field Descriptions
Bit Field Type Reset Description
31-0 MsgValReg R 0h Message Valid Bits (for all message objects)

0 This message object is ignored by the message handler.

1 This message object is configured and will be considered by the message handler.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

28.16.2.21 CAN_IP_MUX21 Register (Offset (x8) = 1B0h, Offset (x16) = D8h) [Reset = 00000000h]

CAN_IP_MUX21 is shown in Figure 28-42 and described in Table 28-30.

Return to the Summary Table.

The IntMux bit determines for each mailbox, which of the two interrupt lines (CANINT0 or CANINT1) will be asserted when the IntPnd bit of that mailbox is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN Control Register. This will also affect the INT0ID or INT1ID flags in the Interrupt Register.

Figure 28-42 CAN_IP_MUX21 Register
313029282726252423222120191817161514131211109876543210
IntMux
R/W-0h
Table 28-30 CAN_IP_MUX21 Register Field Descriptions
Bit Field Type Reset Description
31-0 IntMux R/W 0h Interrupt Mux bits:

0 CANINT0 line is active if corresponding IntPnd flag is one.

1 CANINT1 line is active if corresponding IntPnd flag is one.

Note: Bit 0 is for mailbox 32, Bit 1 is for mailbox 1, Bit 2 is for mailbox 2,..., Bit 31 is for mailbox 31

Reset type: SYSRSn

28.16.2.22 CAN_IF1CMD Register (Offset (x8) = 200h, Offset (x16) = 100h) [Reset = 00000001h]

CAN_IF1CMD is shown in Figure 28-43 and described in Table 28-31.

Return to the Summary Table.

The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and the Message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.

If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. The following points must be borne in mind while writing to this register: (1) Do not write zeros to the whole register. (2) Write to the register in a single 32-bit write or write the upper 16-bits before writing to the lower 16- bits.

Note: While Busy bit is one, IF1/IF2 Register sets are write protected.

Note: For debug support, the auto clear functionality of the IF1/IF2 Command Registers (clear of DMAactive flag by R/W, for devices with DMA support) is disabled during Debug/Suspend mode.

Note: If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, the Message Handler may access an implemented (valid) message object instead.

Figure 28-43 CAN_IF1CMD Register
3130292827262524
RESERVED
R-0h
2322212019181716
DIRMaskArbControlClrIntPndTXRQSTDATA_ADATA_B
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BusyDMAactiveRESERVED
R-0hR/W-0hR-0h
76543210
MSG_NUM
R/W-1h
Table 28-31 CAN_IF1CMD Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23 DIR R/W 0h Write/Read

0 Direction = Read: Transfer direction is from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set. That is, transfer data from the mailbox into the selected IF1/IF2 Message Buffer Registers.

1 Direction = Write: Transfer direction is from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]) . That is, transfer data from the selected IF1/IF2 Message Buffer Registers to the mailbox.

The other bits of IF1/IF2 Command Mask Register have different functions depending on the transfer direction.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
22 Mask R/W 0h Access Mask Bits

0 Mask bits will not be changed

1 (Direction = Read): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set.

1 (Direction = Write): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
21 Arb R/W 0h Access Arbitration Bits

0 Arbitration bits will not be changed

1 (Direction = Read): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1/IF2 Register set to the mes-sage object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
20 Control R/W 0h Access control bits.

If the TxRqst/NewDat bit in this register(Bit [18]) is set, the TxRqst/NewDat bit in the IF1 message control register will be ignored.

0 Control bits will not be changed.

1 (Direction = Read): The message control bits will be transferred from the message object addressed by message number (Bits [7:0]) to the IF1 register set.

1 (Direction = Write): The message control bits will be transferred from the IF1 register set to the
message object addressed by message number (Bits [7:0]).

Note: This bit is write protected by the Busy bit.

Reset type: SYSRSn
19 ClrIntPnd R/W 0h Clear Interrupt Pending Bit

0 IntPnd bit will not be changed

1 (Direction = Read): Clears IntPnd bit in the message object.

1 (Direction = Write): This bit is ignored.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
18 TXRQST R/W 0h Access Transmission Request (TxRqst) / New Data (NewDat) Bit

0 (Direction = Read): NewDat bit will not be changed.
0 (Direction = Write): TxRqst/NewDat bit will be handled according to the Control bit.

1 (Direction = Read): Clears NewDat bit in the message object.
1 (Direction = Write): Sets TxRqst/NewDat in message object.

Note: If a CAN transmission is requested by setting TxRqst/NewDat in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in IF1/IF2 Message Control Register.

Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IF1/IF2 Message Control Register always reflect the status before resetting them.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
17 DATA_A R/W 0h Access Data Bytes 0-3

0 Data Bytes 0-3 will not be changed.

1 (Direction = Read): The Data Bytes 0-3 will be transferred from the message object addressed by the Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 0-3 will be transferred from the IF1/IF2 Register set to the message object addressed by the Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
16 DATA_B R/W 0h Access Data Bytes 4-7

0 Data Bytes 4-7 will not be changed.

1 (Direction = Read): The Data Bytes 4-7 will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 4-7 will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
15 Busy R 0h Busy Flag

0 No transfer between IF1/IF2 Register Set and Message RAM is in progress.

1 Transfer between IF1/IF2 Register Set and Message RAM is in progress.

This bit is set to one after the message number has been written to bits [7:0]. IF1/IF2 Register Set will be write protected. The bit is cleared after read/write action has been finished.

Reset type: SYSRSn
14 DMAactive R/W 0h DMA trigger status due to IF1 update.

0 No IF1 DMA request is active.

1 DMA is requested after a completed transfer between IF1 and the message RAM. The DMA request remains active until the first read or write to one of the IF1 registers
an exception is a write to Message Number (Bits [7:0]) when DMAactive is one.

Note: Due to the auto reset feature of the DMAactive bit, this bit has to be set for each subsequent DMA cycle separately.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
13-8 RESERVED R 0h Reserved
7-0 MSG_NUM R/W 1h Number of message object in Message RAM which is used for data transfer

0x00 Invalid message number

0x01-0x20 Valid message numbers

0x21-0xFF Invalid message numbers

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.23 CAN_IF1MSK Register (Offset (x8) = 208h, Offset (x16) = 104h) [Reset = FFFFFFFFh]

CAN_IF1MSK is shown in Figure 28-44 and described in Table 28-32.

Return to the Summary Table.

The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 28-44 CAN_IF1MSK Register
3130292827262524
MXtdMDirRESERVEDMsk
R/W-1hR/W-1hR-1hR/W-1FFFFFFFh
2322212019181716
Msk
R/W-1FFFFFFFh
15141312111098
Msk
R/W-1FFFFFFFh
76543210
Msk
R/W-1FFFFFFFh
Table 28-32 CAN_IF1MSK Register Field Descriptions
Bit Field Type Reset Description
31 MXtd R/W 1h Mask Extended Identifier

0 The extended identifier bit (Xtd) has no effect on the acceptance filtering.

1 The extended identifier bit (Xtd) is used for acceptance filtering.

When 11-bit ('standard') identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
30 MDir R/W 1h Mask Message Direction

0 The message direction bit (Dir) has no effect on the acceptance filtering.

1 The message direction bit (Dir) is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
29 RESERVED R 1h Reserved
28-0 Msk R/W 1FFFFFFFh Identifier Mask-

0 The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care).

1 The corresponding bit in the identifier of the message object is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.24 CAN_IF1ARB Register (Offset (x8) = 210h, Offset (x16) = 108h) [Reset = 00000000h]

CAN_IF1ARB is shown in Figure 28-45 and described in Table 28-33.

Return to the Summary Table.

The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The Arbitration bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messages and (together with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming messages.

A received message is stored into the valid message object with matching identifier and Direction = receive (Data Frame) or Direction = transmit (Remote Frame).

Extended frames can be stored only in message objects with Xtd = one, standard frames in message objects with Xtd = zero.

If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it is stored into the one with the lowest message number.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 28-45 CAN_IF1ARB Register
3130292827262524
MsgValXtdDirID
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ID
R/W-0h
15141312111098
ID
R/W-0h
76543210
ID
R/W-0h
Table 28-33 CAN_IF1ARB Register Field Descriptions
Bit Field Type Reset Description
31 MsgVal R/W 0h Message Valid

0 The mailbox is disabled. (The message object is ignored by the message handler).

1 The mailbox is enabled. (The message object is to be used by the message handler).

The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets the Init bit in the CAN Control Register.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
30 Xtd R/W 0h Extended Identifier

0 The 11-bit ('standard') Identifier is used for this message object.

1 The 29-bit ('extended') Identifier is used for this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
29 Dir R/W 0h Message Direction

0 Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that frame is stored in this message object.

1 Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = one).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
28-0 ID R/W 0h Message Identifier

ID[28:0] 29-bit Identifier ('Extended Frame')

ID[28:18] 11-bit Identifier ('Standard Frame')

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.25 CAN_IF1MCTL Register (Offset (x8) = 218h, Offset (x16) = 10Ch) [Reset = 00000000h]

CAN_IF1MCTL is shown in Figure 28-46 and described in Table 28-34.

Return to the Summary Table.

The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object. This register has control/status bits pertaining to interrupts, acceptance mask, remote frames and FIFO option.

Figure 28-46 CAN_IF1MCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NewDatMsgLstIntPndUMaskTxIERxIERmtEnTxRqst
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EoBRESERVEDDLC
R/W-0hR-0hR/W-0h
Table 28-34 CAN_IF1MCTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 NewDat R/W 0h New Data

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
14 MsgLst R/W 0h Message Lost (only valid for message objects with direction = receive)

0 No message lost since the last time when this bit was reset by the CPU.

1 The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
13 IntPnd R/W 0h Interrupt Pending

0 This message object is not the source of an interrupt.

1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
12 UMask R/W 0h Use Acceptance Mask

0 Mask ignored

1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering

If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
11 TxIE R/W 0h Transmit Interrupt Enable

0 IntPnd will not be triggered after the successful transmission of a frame.

1 IntPnd will be triggered after the successful transmission of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
10 RxIE R/W 0h Receive Interrupt Enable

0 IntPnd will not be triggered after the successful reception of a frame.

1 IntPnd will be triggered after the successful reception of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
9 RmtEn R/W 0h Remote Enable

0 At the reception of a remote frame, TxRqst is not changed.

1 At the reception of a remote frame, TxRqst is set.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
8 TxRqst R/W 0h Transmit Request

0 This message object is not waiting for a transmission.

1 The transmission of this message object is requested and is not yet done.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
7 EoB R/W 0h End of Block

0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block.

1 The message object is a single message object or the last message object in a FIFO Buffer Block.

Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
6-4 RESERVED R 0h Reserved
3-0 DLC R/W 0h Data length code

0-8 Data frame has 0-8 data bytes.

9-15 Data frame has 8 data bytes.

Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.26 CAN_IF1DATA Register (Offset (x8) = 220h, Offset (x16) = 110h) [Reset = 00000000h]

CAN_IF1DATA is shown in Figure 28-47 and described in Table 28-35.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 28-47 CAN_IF1DATA Register
313029282726252423222120191817161514131211109876543210
Data_3Data_2Data_1Data_0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 28-35 CAN_IF1DATA Register Field Descriptions
Bit Field Type Reset Description
31-24 Data_3 R/W 0h Data Byte 3

Reset type: SYSRSn
23-16 Data_2 R/W 0h Data Byte 2

Reset type: SYSRSn
15-8 Data_1 R/W 0h Data Byte 1

Reset type: SYSRSn
7-0 Data_0 R/W 0h Data Byte 0

Reset type: SYSRSn

28.16.2.27 CAN_IF1DATB Register (Offset (x8) = 228h, Offset (x16) = 114h) [Reset = 00000000h]

CAN_IF1DATB is shown in Figure 28-48 and described in Table 28-36.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 28-48 CAN_IF1DATB Register
313029282726252423222120191817161514131211109876543210
Data_7Data_6Data_5Data_4
R/W-0hR/W-0hR/W-0hR/W-0h
Table 28-36 CAN_IF1DATB Register Field Descriptions
Bit Field Type Reset Description
31-24 Data_7 R/W 0h Data Byte 7

Reset type: SYSRSn
23-16 Data_6 R/W 0h Data Byte 6

Reset type: SYSRSn
15-8 Data_5 R/W 0h Data Byte 5

Reset type: SYSRSn
7-0 Data_4 R/W 0h Data Byte 4

Reset type: SYSRSn

28.16.2.28 CAN_IF2CMD Register (Offset (x8) = 240h, Offset (x16) = 120h) [Reset = 00000001h]

CAN_IF2CMD is shown in Figure 28-49 and described in Table 28-37.

Return to the Summary Table.

The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and the Message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.

If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. The following points must be borne in mind while writing to this register: (1) Do not write zeros to the whole register. (2) Write to the register in a single 32-bit write or write the upper 16-bits before writing to the lower 16- bits.

Note: While Busy bit is one, IF1/IF2 Register sets are write protected.

Note: For debug support, the auto clear functionality of the IF1/IF2 Command Registers (clear of DMAactive flag by R/W, for devices with DMA support) is disabled during Debug/Suspend mode.

Note: If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, the Message Handler may access an implemented (valid) message object instead.

Figure 28-49 CAN_IF2CMD Register
3130292827262524
RESERVED
R-0h
2322212019181716
DIRMaskArbControlClrIntPndTxRqstDATA_ADATA_B
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BusyDMAactiveRESERVED
R-0hR/W-0hR-0h
76543210
MSG_NUM
R/W-1h
Table 28-37 CAN_IF2CMD Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23 DIR R/W 0h Write/Read

0 Direction = Read: Transfer direction is from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set. That is, transfer data from the mailbox into the selected IF1/IF2 Message Buffer Registers.

1 Direction = Write: Transfer direction is from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]) . That is, transfer data from the selected IF1/IF2 Message Buffer Registers to the mailbox.

The other bits of IF1/IF2 Command Mask Register have different functions depending on the transfer direction.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
22 Mask R/W 0h Access Mask Bits

0 Mask bits will not be changed

1 (Direction = Read): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set.

1 (Direction = Write): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
21 Arb R/W 0h Access Arbitration Bits

0 Arbitration bits will not be changed

1 (Direction = Read): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1/IF2 Register set to the mes-sage object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
20 Control R/W 0h Access control bits.

If the TxRqst/NewDat bit in this register(Bit [18]) is set, the TxRqst/NewDat bit in the IF1 message control register will be ignored.

0 Control bits will not be changed.

1 (Direction = Read): The message control bits will be transferred from the message object addressed by message number (Bits [7:0]) to the IF1 register set.

1 (Direction = Write): The message control bits will be transferred from the IF1 register set to the
message object addressed by message number (Bits [7:0]).

Note: This bit is write protected by the Busy bit.

Reset type: SYSRSn
19 ClrIntPnd R/W 0h Clear Interrupt Pending Bit

0 IntPnd bit will not be changed

1 (Direction = Read): Clears IntPnd bit in the message object.

1 (Direction = Write): This bit is ignored.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
18 TxRqst R/W 0h Access Transmission Request (TxRqst) / New Data (NewDat) Bit

0 (Direction = Read): NewDat bit will not be changed.
0 (Direction = Write): TxRqst/NewDat bit will be handled according to the Control bit.

1 (Direction = Read): Clears NewDat bit in the message object.
1 (Direction = Write): Sets TxRqst/NewDat in message object.

Note: If a CAN transmission is requested by setting TxRqst/NewDat in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in IF1/IF2 Message Control Register.

Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IF1/IF2 Message Control Register always reflect the status before resetting them.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
17 DATA_A R/W 0h Access Data Bytes 0-3

0 Data Bytes 0-3 will not be changed.

1 (Direction = Read): The Data Bytes 0-3 will be transferred from the message object addressed by the Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 0-3 will be transferred from the IF1/IF2 Register set to the message object addressed by the Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
16 DATA_B R/W 0h Access Data Bytes 4-7

0 Data Bytes 4-7 will not be changed.

1 (Direction = Read): The Data Bytes 4-7 will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 4-7 will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
15 Busy R 0h Busy Flag

0 No transfer between IF1/IF2 Register Set and Message RAM is in progress.

1 Transfer between IF1/IF2 Register Set and Message RAM is in progress.

This bit is set to one after the message number has been written to bits [7:0]. IF1/IF2 Register Set will be write protected. The bit is cleared after read/write action has been finished.

Reset type: SYSRSn
14 DMAactive R/W 0h DMA trigger status due to IF1 update.

0 No IF1 DMA request is active.

1 DMA is requested after a completed transfer between IF1 and the message RAM. The DMA request remains active until the first read or write to one of the IF1 registers
an exception is a write to Message Number (Bits [7:0]) when DMAactive is one.

Note: Due to the auto reset feature of the DMAactive bit, this bit has to be set for each subsequent DMA cycle separately.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
13-8 RESERVED R 0h Reserved
7-0 MSG_NUM R/W 1h Number of message object in Message RAM which is used for data transfer

0x00 Invalid message number

0x01-0x20 Valid message numbers

0x21-0xFF Invalid message numbers

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.29 CAN_IF2MSK Register (Offset (x8) = 248h, Offset (x16) = 124h) [Reset = FFFFFFFFh]

CAN_IF2MSK is shown in Figure 28-50 and described in Table 28-38.

Return to the Summary Table.

The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 28-50 CAN_IF2MSK Register
3130292827262524
MXtdMDirRESERVEDMsk
R/W-1hR/W-1hR-1hR/W-1FFFFFFFh
2322212019181716
Msk
R/W-1FFFFFFFh
15141312111098
Msk
R/W-1FFFFFFFh
76543210
Msk
R/W-1FFFFFFFh
Table 28-38 CAN_IF2MSK Register Field Descriptions
Bit Field Type Reset Description
31 MXtd R/W 1h Mask Extended Identifier

0 The extended identifier bit (Xtd) has no effect on the acceptance filtering.

1 The extended identifier bit (Xtd) is used for acceptance filtering.

When 11-bit ('standard') identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
30 MDir R/W 1h Mask Message Direction

0 The message direction bit (Dir) has no effect on the acceptance filtering.

1 The message direction bit (Dir) is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
29 RESERVED R 1h Reserved
28-0 Msk R/W 1FFFFFFFh Identifier Mask

0 The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care).

1 The corresponding bit in the identifier of the message object is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.30 CAN_IF2ARB Register (Offset (x8) = 250h, Offset (x16) = 128h) [Reset = 00000000h]

CAN_IF2ARB is shown in Figure 28-51 and described in Table 28-39.

Return to the Summary Table.

The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The Arbitration bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messages and (together with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming messages.

A received message is stored into the valid message object with matching identifier and Direction = receive (Data Frame) or Direction = transmit (Remote Frame).

Extended frames can be stored only in message objects with Xtd = one, standard frames in message objects with Xtd = zero.

If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it is stored into the one with the lowest message number.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 28-51 CAN_IF2ARB Register
3130292827262524
MsgValXtdDirID
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ID
R/W-0h
15141312111098
ID
R/W-0h
76543210
ID
R/W-0h
Table 28-39 CAN_IF2ARB Register Field Descriptions
Bit Field Type Reset Description
31 MsgVal R/W 0h Message Valid

0 The mailbox is disabled. (The message object is ignored by the message handler).

1 The mailbox is enabled. (The message object is to be used by the message handler).

The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets the Init bit in the CAN Control Register.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
30 Xtd R/W 0h Extended Identifier

0 The 11-bit ('standard') Identifier is used for this message object.

1 The 29-bit ('extended') Identifier is used for this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
29 Dir R/W 0h Message Direction

0 Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that frame is stored in this message object.

1 Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = one).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
28-0 ID R/W 0h Message Identifier

ID[28:0] 29-bit Identifier ('Extended Frame')

ID[28:18] 11-bit Identifier ('Standard Frame')

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.31 CAN_IF2MCTL Register (Offset (x8) = 258h, Offset (x16) = 12Ch) [Reset = 00000000h]

CAN_IF2MCTL is shown in Figure 28-52 and described in Table 28-40.

Return to the Summary Table.

The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object. This register has control/status bits pertaining to interrupts, acceptance mask, remote frames and FIFO option.

Figure 28-52 CAN_IF2MCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NewDatMsgLstIntPndUMaskTxIERxIERmtEnTxRqst
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EoBRESERVEDDLC
R/W-0hR-0hR/W-0h
Table 28-40 CAN_IF2MCTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 NewDat R/W 0h New Data

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
14 MsgLst R/W 0h Message Lost (only valid for message objects with direction = receive)

0 No message lost since the last time when this bit was reset by the CPU.

1 The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
13 IntPnd R/W 0h Interrupt Pending

0 This message object is not the source of an interrupt.

1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
12 UMask R/W 0h Use Acceptance Mask

0 Mask ignored

1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering

If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
11 TxIE R/W 0h Transmit Interrupt Enable

0 IntPnd will not be triggered after the successful transmission of a frame.

1 IntPnd will be triggered after the successful transmission of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
10 RxIE R/W 0h Receive Interrupt Enable

0 IntPnd will not be triggered after the successful reception of a frame.

1 IntPnd will be triggered after the successful reception of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
9 RmtEn R/W 0h Remote Enable

0 At the reception of a remote frame, TxRqst is not changed.

1 At the reception of a remote frame, TxRqst is set.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
8 TxRqst R/W 0h Transmit Request

0 This message object is not waiting for a transmission.

1 The transmission of this message object is requested and is not yet done.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
7 EoB R/W 0h End of Block

0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block.

1 The message object is a single message object or the last message object in a FIFO Buffer Block.

Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn
6-4 RESERVED R 0h Reserved
3-0 DLC R/W 0h Data length code

0-8 Data frame has 0-8 data bytes.

9-15 Data frame has 8 data bytes.

Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28.16.2.32 CAN_IF2DATA Register (Offset (x8) = 260h, Offset (x16) = 130h) [Reset = 00000000h]

CAN_IF2DATA is shown in Figure 28-53 and described in Table 28-41.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 28-53 CAN_IF2DATA Register
313029282726252423222120191817161514131211109876543210
Data_3Data_2Data_1Data_0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 28-41 CAN_IF2DATA Register Field Descriptions
Bit Field Type Reset Description
31-24 Data_3 R/W 0h Data Byte 3

Reset type: SYSRSn
23-16 Data_2 R/W 0h Data Byte 2

Reset type: SYSRSn
15-8 Data_1 R/W 0h Data Byte 1

Reset type: SYSRSn
7-0 Data_0 R/W 0h Data Byte 0

Reset type: SYSRSn

28.16.2.33 CAN_IF2DATB Register (Offset (x8) = 268h, Offset (x16) = 134h) [Reset = 00000000h]

CAN_IF2DATB is shown in Figure 28-54 and described in Table 28-42.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 28-54 CAN_IF2DATB Register
313029282726252423222120191817161514131211109876543210
Data_7Data_6Data_5Data_4
R/W-0hR/W-0hR/W-0hR/W-0h
Table 28-42 CAN_IF2DATB Register Field Descriptions
Bit Field Type Reset Description
31-24 Data_7 R/W 0h Data Byte 7

Reset type: SYSRSn
23-16 Data_6 R/W 0h Data Byte 6

Reset type: SYSRSn
15-8 Data_5 R/W 0h Data Byte 5

Reset type: SYSRSn
7-0 Data_4 R/W 0h Data Byte 4

Reset type: SYSRSn

28.16.2.34 CAN_IF3OBS Register (Offset (x8) = 280h, Offset (x16) = 140h) [Reset = 00000000h]

CAN_IF3OBS is shown in Figure 28-55 and described in Table 28-43.

Return to the Summary Table.

The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from Message RAM by CPU.

The observation flags (Bits [4:0]) in the IF3 Observation register are used to determine, which data sections of the IF3 Interface Register set have to be read in order to complete a DMA read cycle. After all marked data sections are read, the DCAN is enabled to update the IF3 Interface Register set with new data.

Any access order of single bytes or half-words is supported. When using byte or half-word accesses, a data section is marked as completed, if all bytes are read.

Note: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses.

A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables updating of IF3 Interface Register set with new data. To avoid data inconsistency, the DMA controller should be disabled before reconfiguring IF3 observation register. The status of the current read-cycle can be observed via status flags (Bits [12:8]).

With this, the observation status bits and the IF3Upd bit could be used by the application to realize the notification about new IF3 content in polling or interrupt mode

Figure 28-55 CAN_IF3OBS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
IF3UpdRESERVEDIF3SDBIF3SDAIF3SCIF3SAIF3SM
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDData_BData_ACtrlArbMask
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 28-43 CAN_IF3OBS Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 IF3Upd R 0h IF3 Update Data

0 No new data has been loaded since last IF3 read.

1 New data has been loaded since last IF3 read.

Reset type: SYSRSn
14-13 RESERVED R 0h Reserved
12 IF3SDB R 0h IF3 Status of Data B read access

0 All Data B bytes are already read out, or are not marked to be read.

1 Data B section has still data to be read out.

Reset type: SYSRSn
11 IF3SDA R 0h IF3 Status of Data A read access

0 All Data A bytes are already read out, or are not marked to be read.

1 Data A section has still data to be read out.

Reset type: SYSRSn
10 IF3SC R 0h IF3 Status of Control bits read access

0 All Control section bytes are already read out, or are not marked to be read.

1 Control section has still data to be read out.

Reset type: SYSRSn
9 IF3SA R 0h IF3 Status of Arbitration data read access

0 All Arbitration data bytes are already read out, or are not marked to be read.

1 Arbitration section has still data to be read out.

Reset type: SYSRSn
8 IF3SM R 0h IF3 Status of Mask data read access

0 All Mask data bytes are already read out, or are not marked to be read.

1 Mask section has still data to be read out.

Reset type: SYSRSn
7-5 RESERVED R 0h Reserved
4 Data_B R/W 0h Data B read observation

0 Data B section not to be read.

1 Data B section has to be read to enable next IF3 update.

Reset type: SYSRSn
3 Data_A R/W 0h Data A read observation

0 Data A section not to be read.

1 Data A section has to be read to enable next IF3 update.

Reset type: SYSRSn
2 Ctrl R/W 0h Ctrl read observation

0 Ctrl section not to be read.

1 Ctrl section has to be read to enable next IF3 update.

Reset type: SYSRSn
1 Arb R/W 0h Arbitration data read observation

0 Arbitration data not to be read.

1 Arbitration data has to be read to enable next IF3 update.

Reset type: SYSRSn
0 Mask R/W 0h Mask data read observation

0 Mask data not to be read.

1 Mask data has to be read to enable next IF3 update.

Reset type: SYSRSn

28.16.2.35 CAN_IF3MSK Register (Offset (x8) = 288h, Offset (x16) = 144h) [Reset = FFFFFFFFh]

CAN_IF3MSK is shown in Figure 28-56 and described in Table 28-44.

Return to the Summary Table.

This register provides a window to the acceptance mask for the chosen mailbox.

Figure 28-56 CAN_IF3MSK Register
3130292827262524
MXtdMDirRESERVEDMsk
R-1hR-1hR-1hR-1FFFFFFFh
2322212019181716
Msk
R-1FFFFFFFh
15141312111098
Msk
R-1FFFFFFFh
76543210
Msk
R-1FFFFFFFh
Table 28-44 CAN_IF3MSK Register Field Descriptions
Bit Field Type Reset Description
31 MXtd R 1h Mask Extended Identifier

0 The extended identifier bit (Xtd) has no effect on the acceptance filtering.

1 The extended identifier bit (Xtd) is used for acceptance filtering.

Note: When 11-bit ('standard') identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered.

Reset type: SYSRSn
30 MDir R 1h Mask Message Direction

0 The message direction bit (Dir) has no effect on the acceptance filtering.

1 The message direction bit (Dir) is used for acceptance filtering.

Reset type: SYSRSn
29 RESERVED R 1h Reserved
28-0 Msk R 1FFFFFFFh Identifier Mask Identifier Mask

0 The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care).

1 The corresponding bit in the identifier of the message object is used for acceptance filtering. Identifier Mask

Reset type: SYSRSn

28.16.2.36 CAN_IF3ARB Register (Offset (x8) = 290h, Offset (x16) = 148h) [Reset = 00000000h]

CAN_IF3ARB is shown in Figure 28-57 and described in Table 28-45.

Return to the Summary Table.

The bits of the IF3 Arbitration Register mirrors the arbitration bits of a message object.

Figure 28-57 CAN_IF3ARB Register
3130292827262524
MsgValXtdDirID
R-0hR-0hR-0hR-0h
2322212019181716
ID
R-0h
15141312111098
ID
R-0h
76543210
ID
R-0h
Table 28-45 CAN_IF3ARB Register Field Descriptions
Bit Field Type Reset Description
31 MsgVal R 0h Message Valid

0 The message object is ignored by the message handler.

1 The message object is to be used by the message handler.

The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register.

Reset type: SYSRSn
30 Xtd R 0h Extended Identifier

0 The 11-bit ('standard') Identifier is used for this message object.

1 The 29-bit ('extended') Identifier is used for this message object.

Reset type: SYSRSn
29 Dir R 0h Message Direction

0 Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that message is stored in this message object.

1 Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = one).

Reset type: SYSRSn
28-0 ID R 0h Message Identifier

ID[28:0] 29-bit Identifier ('Extended Frame')

ID[28:18] 11-bit Identifier ('Standard Frame')

Reset type: SYSRSn

28.16.2.37 CAN_IF3MCTL Register (Offset (x8) = 298h, Offset (x16) = 14Ch) [Reset = 00000000h]

CAN_IF3MCTL is shown in Figure 28-58 and described in Table 28-46.

Return to the Summary Table.

The bits of the IF3 Message Control Register mirrors the message control bits of a message object.

Figure 28-58 CAN_IF3MCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NewDatMsgLstIntPndUMaskTxIERxIERmtEnTxRqst
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
EoBRESERVEDDLC
R-0hR-0hR-0h
Table 28-46 CAN_IF3MCTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 NewDat R 0h New Data

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Reset type: SYSRSn
14 MsgLst R 0h Message Lost (only valid for message objects with direction = receive)

0 No message lost since the last time when this bit was reset by the CPU.

1 The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten.

Reset type: SYSRSn
13 IntPnd R 0h Interrupt Pending

0 This message object is not the source of an interrupt.

1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

Reset type: SYSRSn
12 UMask R 0h Use Acceptance Mask

0 Mask ignored

1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering

If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one.

Reset type: SYSRSn
11 TxIE R 0h Transmit Interrupt Enable

0 IntPnd will not be triggered after the successful transmission of a frame.

1 IntPnd will be triggered after the successful transmission of a frame.

Reset type: SYSRSn
10 RxIE R 0h Receive Interrupt Enable

0 IntPnd will not be triggered after the successful reception of a frame.

1 IntPnd will be triggered after the successful reception of a frame.

Reset type: SYSRSn
9 RmtEn R 0h Remote Enable

0 At the reception of a remote frame, TxRqst is not changed.

1 At the reception of a remote frame, TxRqst is set.

Reset type: SYSRSn
8 TxRqst R 0h Transmit Request

0 This message object is not waiting for a transmission.

1 The transmission of this message object is requested and is not yet done.

Reset type: SYSRSn
7 EoB R 0h End of Block

0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block.

1 The message object is a single message object or the last message object in a FIFO Buffer Block.

Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one.

Reset type: SYSRSn
6-4 RESERVED R 0h Reserved
3-0 DLC R 0h Data length code

0-8 Data frame has 0-8 data bytes.

9-15 Data frame has 8 data bytes.

Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message.

Reset type: SYSRSn

28.16.2.38 CAN_IF3DATA Register (Offset (x8) = 2A0h, Offset (x16) = 150h) [Reset = 00000000h]

CAN_IF3DATA is shown in Figure 28-59 and described in Table 28-47.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message.

Figure 28-59 CAN_IF3DATA Register
313029282726252423222120191817161514131211109876543210
Data_3Data_2Data_1Data_0
R-0hR-0hR-0hR-0h
Table 28-47 CAN_IF3DATA Register Field Descriptions
Bit Field Type Reset Description
31-24 Data_3 R 0h Data Byte 3

Reset type: SYSRSn
23-16 Data_2 R 0h Data Byte 2

Reset type: SYSRSn
15-8 Data_1 R 0h Data Byte 1

Reset type: SYSRSn
7-0 Data_0 R 0h Data Byte 0

Reset type: SYSRSn

28.16.2.39 CAN_IF3DATB Register (Offset (x8) = 2A8h, Offset (x16) = 154h) [Reset = 00000000h]

CAN_IF3DATB is shown in Figure 28-60 and described in Table 28-48.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message.

Figure 28-60 CAN_IF3DATB Register
313029282726252423222120191817161514131211109876543210
Data_7Data_6Data_5Data_4
R-0hR-0hR-0hR-0h
Table 28-48 CAN_IF3DATB Register Field Descriptions
Bit Field Type Reset Description
31-24 Data_7 R 0h Data Byte 7

Reset type: SYSRSn
23-16 Data_6 R 0h Data Byte 6

Reset type: SYSRSn
15-8 Data_5 R 0h Data Byte 5

Reset type: SYSRSn
7-0 Data_4 R 0h Data Byte 4

Reset type: SYSRSn

28.16.2.40 CAN_IF3UPD Register (Offset (x8) = 2C0h, Offset (x16) = 160h) [Reset = 00000000h]

CAN_IF3UPD is shown in Figure 28-61 and described in Table 28-49.

Return to the Summary Table.

The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UpdEn flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set. Note: IF3 Update enable should not be set for transmit objects.

Figure 28-61 CAN_IF3UPD Register
313029282726252423222120191817161514131211109876543210
IF3UpdEn
R/W-0h
Table 28-49 CAN_IF3UPD Register Field Descriptions
Bit Field Type Reset Description
31-0 IF3UpdEn R/W 0h IF3 Update Enabled (for all message objects)

0 Automatic IF3 update is disabled for this message object.

1 Automatic IF3 update is enabled for this message object. A message object is scheduled to be copied to IF3 register set, if NewDat flag of the message object is active.

Reset type: SYSRSn