SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
The required frequency tolerance for the DCAN and MCAN bit clock depends on the bit timing setup and network configuration, and can be as tight as 0.1%. Since the main system clock (in the form of SYSCLK) can not be precise enough, the bit clock can also be connected to XTAL, AUXCLKIN and PLLRAWCLK using the CLKSRCCTL2 register. There is an independent selection for each CAN module. See the CLKSRCCTL2 register for the valid options for the MCAN and DCAN.
To maintain correct operation, the frequency of the CAN bit clock must be less than or equal to the SYSCLK frequency.