SPRUIX1B October 2022 – April 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137
Table 3-20 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS registers. All register offset addresses not listed in Table 3-20 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
20h | MAVFLG | Master Access Violation Flag Register | Go | |
22h | MAVSET | Master Access Violation Flag Set Register | EALLOW | Go |
24h | MAVCLR | Master Access Violation Flag Clear Register | EALLOW | Go |
26h | MAVINTEN | Master Access Violation Interrupt Enable Register | EALLOW | Go |
28h | MCPUFAVADDR | Master CPU Fetch Access Violation Address | Go | |
2Ah | MCPUWRAVADDR | Master CPU Write Access Violation Address | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-21 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
MAVFLG is shown in Figure 3-18 and described in Table 3-22.
Return to the Summary Table.
Master Access Violation Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPUWRITE | CPUFETCH | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | CPUWRITE | R | 0h | Master CPU Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
0 | CPUFETCH | R | 0h | Master CPU Fetch Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
MAVSET is shown in Figure 3-19 and described in Table 3-23.
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Master Access Violation Flag Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPUWRITE | CPUFETCH | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | CPUWRITE | R-0/W1S | 0h | 0: No action. 1: CPU Write Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
0 | CPUFETCH | R-0/W1S | 0h | 0: No action. 1: CPU Fetch Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
MAVCLR is shown in Figure 3-20 and described in Table 3-24.
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Master Access Violation Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPUWRITE | CPUFETCH | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | CPUWRITE | R-0/W1S | 0h | 0: No action. 1: CPU Write Access Violation Flag in MAVFLG register will be cleared . Reset type: SYSRSn |
0 | CPUFETCH | R-0/W1S | 0h | 0: No action. 1: CPU Fetch Access Violation Flag in MAVFLG register will be cleared. Reset type: SYSRSn |
MAVINTEN is shown in Figure 3-21 and described in Table 3-25.
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Master Access Violation Interrupt Enable Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPUWRITE | CPUFETCH | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | CPUWRITE | R/W | 0h | 0: CPU Write Access Violation Interrupt is disabled. 1: CPU Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
0 | CPUFETCH | R/W | 0h | 0: CPU Fetch Access Violation Interrupt is disabled. 1: CPU Fetch Access Violation Interrupt is enabled. Reset type: SYSRSn |
MCPUFAVADDR is shown in Figure 3-22 and described in Table 3-26.
Return to the Summary Table.
Master CPU Fetch Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCPUFAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MCPUFAVADDR | R | 0h | This register captures the address location for which master CPU fetch access violation occurred. Reset type: SYSRSn |
MCPUWRAVADDR is shown in Figure 3-23 and described in Table 3-27.
Return to the Summary Table.
Master CPU Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCPUWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MCPUWRAVADDR | R | 0h | This register captures the address location for which master CPU write access violation occurred. Reset type: SYSRSn |