SPRUIX1B October 2022 – April 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137
Table 8-10 lists the memory-mapped registers for the GPIO_CTRL_REGS registers. All register offset addresses not listed in Table 8-10 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | GPACTRL | GPIO A Qualification Sampling Period Control (GPIO0 to 31) | EALLOW | Go |
2h | GPAQSEL1 | GPIO A Qualifier Select 1 Register (GPIO0 to 15) | EALLOW | Go |
4h | GPAQSEL2 | GPIO A Qualifier Select 2 Register (GPIO16 to 31) | EALLOW | Go |
6h | GPAMUX1 | GPIO A Mux 1 Register (GPIO0 to 15) | EALLOW | Go |
8h | GPAMUX2 | GPIO A Mux 2 Register (GPIO16 to 31) | EALLOW | Go |
Ah | GPADIR | GPIO A Direction Register (GPIO0 to 31) | EALLOW | Go |
Ch | GPAPUD | GPIO A Pull Up Disable Register (GPIO0 to 31) | EALLOW | Go |
10h | GPAINV | GPIO A Input Polarity Invert Registers (GPIO0 to 31) | EALLOW | Go |
12h | GPAODR | GPIO A Open Drain Output Register (GPIO0 to GPIO31) | EALLOW | Go |
14h | GPAAMSEL | GPIO A Analog Mode Select register (GPIO0 to GPIO31) | EALLOW | Go |
20h | GPAGMUX1 | GPIO A Peripheral Group Mux (GPIO0 to 15) | EALLOW | Go |
22h | GPAGMUX2 | GPIO A Peripheral Group Mux (GPIO16 to 31) | EALLOW | Go |
3Ch | GPALOCK | GPIO A Lock Configuration Register (GPIO0 to 31) | EALLOW | Go |
3Eh | GPACR | GPIO A Lock Commit Register (GPIO0 to 31) | EALLOW | Go |
40h | GPBCTRL | GPIO B Qualification Sampling Period Control (GPIO32 to 63) | EALLOW | Go |
42h | GPBQSEL1 | GPIO B Qualifier Select 1 Register (GPIO32 to 47) | EALLOW | Go |
46h | GPBMUX1 | GPIO B Mux 1 Register (GPIO32 to 47) | EALLOW | Go |
4Ah | GPBDIR | GPIO B Direction Register (GPIO32 to 63) | EALLOW | Go |
4Ch | GPBPUD | GPIO B Pull Up Disable Register (GPIO32 to 63) | EALLOW | Go |
50h | GPBINV | GPIO B Input Polarity Invert Registers (GPIO32 to 63) | EALLOW | Go |
52h | GPBODR | GPIO B Open Drain Output Register (GPIO32 to GPIO63) | EALLOW | Go |
60h | GPBGMUX1 | GPIO B Peripheral Group Mux (GPIO32 to 47) | EALLOW | Go |
7Ch | GPBLOCK | GPIO B Lock Configuration Register (GPIO32 to 63) | EALLOW | Go |
7Eh | GPBCR | GPIO B Lock Commit Register (GPIO32 to 63) | EALLOW | Go |
1C0h | GPHCTRL | GPIO H Qualification Sampling Period Control (GPIO224 to 255) | EALLOW | Go |
1C2h | GPHQSEL1 | GPIO H Qualifier Select 1 Register (GPIO224 to 239) | EALLOW | Go |
1C4h | GPHQSEL2 | GPIO H Qualifier Select 2 Register (GPIO240 to 255) | EALLOW | Go |
1C6h | GPHMUX1 | GPIO H Mux 1 Register (GPIO224 to 239) | EALLOW | Go |
1C8h | GPHMUX2 | GPIO H Mux 2 Register (GPIO240 to 255) | EALLOW | Go |
1CAh | GPHDIR | GPIO H Direction Register (GPIO224 to 255) | EALLOW | Go |
1CCh | GPHPUD | GPIO H Pull Up Disable Register (GPIO224 to 255) | EALLOW | Go |
1D0h | GPHINV | GPIO H Input Polarity Invert Registers (GPIO224 to 255) | EALLOW | Go |
1D2h | GPHODR | GPIO H Open Drain Output Register (GPIO224 to GPIO255) | EALLOW | Go |
1D4h | GPHAMSEL | GPIO H Analog Mode Select register (GPIO224 to GPIO255) | EALLOW | Go |
1E0h | GPHGMUX1 | GPIO H Peripheral Group Mux (GPIO224 to 239) | EALLOW | Go |
1E2h | GPHGMUX2 | GPIO H Peripheral Group Mux (GPIO240 to 255) | EALLOW | Go |
1FCh | GPHLOCK | GPIO H Lock Configuration Register (GPIO224 to 255) | EALLOW | Go |
1FEh | GPHCR | GPIO H Lock Commit Register (GPIO224 to 255) | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-11 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
GPACTRL is shown in Figure 8-4 and described in Table 8-12.
Return to the Summary Table.
GPIO A Qualification Sampling Period Control (GPIO0 to 31)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUALPRD3 | QUALPRD2 | QUALPRD1 | QUALPRD0 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | QUALPRD3 | R/W | 0h | Qualification sampling period for GPIO24 to GPIO31: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
23-16 | QUALPRD2 | R/W | 0h | Qualification sampling period for GPIO16 to GPIO23: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
15-8 | QUALPRD1 | R/W | 0h | Qualification sampling period for GPIO8 to GPIO15: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
7-0 | QUALPRD0 | R/W | 0h | Qualification sampling period for GPIO0 to GPIO7: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
GPAQSEL1 is shown in Figure 8-5 and described in Table 8-13.
Return to the Summary Table.
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | GPIO13 | R/W | 0h | Select input qualification type for GPIO13: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
25-24 | GPIO12 | R/W | 0h | Select input qualification type for GPIO12: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
23-22 | GPIO11 | R/W | 0h | Select input qualification type for GPIO11: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
21-20 | GPIO10 | R/W | 0h | Select input qualification type for GPIO10: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
19-18 | GPIO9 | R/W | 0h | Select input qualification type for GPIO9: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
17-16 | GPIO8 | R/W | 0h | Select input qualification type for GPIO8: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
15-14 | GPIO7 | R/W | 0h | Select input qualification type for GPIO7: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
13-12 | GPIO6 | R/W | 0h | Select input qualification type for GPIO6: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
11-10 | GPIO5 | R/W | 0h | Select input qualification type for GPIO5: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
9-8 | GPIO4 | R/W | 0h | Select input qualification type for GPIO4: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
7-6 | GPIO3 | R/W | 0h | Select input qualification type for GPIO3: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
5-4 | GPIO2 | R/W | 0h | Select input qualification type for GPIO2: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
3-2 | GPIO1 | R/W | 0h | Select input qualification type for GPIO1: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
1-0 | GPIO0 | R/W | 0h | Select input qualification type for GPIO0: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
GPAQSEL2 is shown in Figure 8-6 and described in Table 8-14.
Return to the Summary Table.
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | GPIO29 | R/W | 0h | Select input qualification type for GPIO29: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
25-24 | GPIO28 | R/W | 0h | Select input qualification type for GPIO28: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | GPIO24 | R/W | 0h | Select input qualification type for GPIO24: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
15-14 | GPIO23 | R/W | 0h | Select input qualification type for GPIO23: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
13-12 | GPIO22 | R/W | 0h | Select input qualification type for GPIO22: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
11-10 | GPIO21 | R/W | 0h | Select input qualification type for GPIO21: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
9-8 | GPIO20 | R/W | 0h | Select input qualification type for GPIO20: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
7-6 | GPIO19 | R/W | 0h | Select input qualification type for GPIO19: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
5-4 | GPIO18 | R/W | 0h | Select input qualification type for GPIO18: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
3-2 | GPIO17 | R/W | 0h | Select input qualification type for GPIO17: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
1-0 | GPIO16 | R/W | 0h | Select input qualification type for GPIO16: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
GPAMUX1 is shown in Figure 8-7 and described in Table 8-15.
Return to the Summary Table.
GPIO A Mux 1 Register (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | GPIO13 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
25-24 | GPIO12 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
23-22 | GPIO11 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
21-20 | GPIO10 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
19-18 | GPIO9 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
17-16 | GPIO8 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
15-14 | GPIO7 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
13-12 | GPIO6 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
11-10 | GPIO5 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
9-8 | GPIO4 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
7-6 | GPIO3 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | GPIO2 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | GPIO1 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
1-0 | GPIO0 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPAMUX2 is shown in Figure 8-8 and described in Table 8-16.
Return to the Summary Table.
GPIO A Mux 2 Register (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | GPIO29 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
25-24 | GPIO28 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | GPIO24 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
15-14 | GPIO23 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
13-12 | GPIO22 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
11-10 | GPIO21 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
9-8 | GPIO20 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
7-6 | GPIO19 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | GPIO18 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | GPIO17 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
1-0 | GPIO16 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPADIR is shown in Figure 8-9 and described in Table 8-17.
Return to the Summary Table.
GPIO A Direction Register (GPIO0 to 31)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | GPIO29 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
28 | GPIO28 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | GPIO24 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
23 | GPIO23 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
22 | GPIO22 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
21 | GPIO21 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
20 | GPIO20 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
19 | GPIO19 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
18 | GPIO18 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
17 | GPIO17 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
16 | GPIO16 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | GPIO13 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
12 | GPIO12 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
11 | GPIO11 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
10 | GPIO10 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
9 | GPIO9 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
8 | GPIO8 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
7 | GPIO7 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
6 | GPIO6 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
5 | GPIO5 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
4 | GPIO4 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
3 | GPIO3 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
2 | GPIO2 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
1 | GPIO1 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
0 | GPIO0 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
GPAPUD is shown in Figure 8-10 and described in Table 8-18.
Return to the Summary Table.
GPIO A Pull Up Disable Register (GPIO0 to 31)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30 | RESERVED | R/W | 1h | Reserved |
29 | GPIO29 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
28 | GPIO28 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
27 | RESERVED | R/W | 1h | Reserved |
26 | RESERVED | R/W | 1h | Reserved |
25 | RESERVED | R/W | 1h | Reserved |
24 | GPIO24 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
23 | GPIO23 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
22 | GPIO22 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
21 | GPIO21 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
20 | GPIO20 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
19 | GPIO19 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
18 | GPIO18 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
17 | GPIO17 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
16 | GPIO16 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
15 | RESERVED | R/W | 1h | Reserved |
14 | RESERVED | R/W | 1h | Reserved |
13 | GPIO13 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
12 | GPIO12 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
11 | GPIO11 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
10 | GPIO10 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
9 | GPIO9 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
8 | GPIO8 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
7 | GPIO7 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
6 | GPIO6 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
5 | GPIO5 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
4 | GPIO4 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
3 | GPIO3 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
2 | GPIO2 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
1 | GPIO1 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
0 | GPIO0 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
GPAINV is shown in Figure 8-11 and described in Table 8-19.
Return to the Summary Table.
GPIO A Input Polarity Invert Registers (GPIO0 to 31)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | GPIO29 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
28 | GPIO28 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | GPIO24 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
23 | GPIO23 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
22 | GPIO22 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
21 | GPIO21 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
20 | GPIO20 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
19 | GPIO19 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
18 | GPIO18 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
17 | GPIO17 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
16 | GPIO16 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | GPIO13 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
12 | GPIO12 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
11 | GPIO11 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
10 | GPIO10 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
9 | GPIO9 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
8 | GPIO8 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
7 | GPIO7 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
6 | GPIO6 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
5 | GPIO5 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
4 | GPIO4 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
3 | GPIO3 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
2 | GPIO2 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
1 | GPIO1 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
0 | GPIO0 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
GPAODR is shown in Figure 8-12 and described in Table 8-20.
Return to the Summary Table.
GPIO A Open Drain Output Register (GPIO0 to GPIO31)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | GPIO29 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
28 | GPIO28 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | GPIO24 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
23 | GPIO23 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
22 | GPIO22 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
21 | GPIO21 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
20 | GPIO20 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
19 | GPIO19 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
18 | GPIO18 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
17 | GPIO17 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
16 | GPIO16 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | GPIO13 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
12 | GPIO12 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
11 | GPIO11 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
10 | GPIO10 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
9 | GPIO9 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
8 | GPIO8 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
7 | GPIO7 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
6 | GPIO6 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
5 | GPIO5 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
4 | GPIO4 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
3 | GPIO3 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
2 | GPIO2 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
1 | GPIO1 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
0 | GPIO0 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
GPAAMSEL is shown in Figure 8-13 and described in Table 8-21.
Return to the Summary Table.
GPIO A Analog Mode Select register (GPIO0 to GPIO31)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | GPIO28 | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO21 | GPIO20 | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30 | RESERVED | R/W | 1h | Reserved |
29 | RESERVED | R/W | 1h | Reserved |
28 | GPIO28 | R/W | 1h | Analog Mode select for this pin Reset type: SYSRSn |
27 | RESERVED | R/W | 1h | Reserved |
26 | RESERVED | R/W | 1h | Reserved |
25 | RESERVED | R/W | 1h | Reserved |
24 | RESERVED | R/W | 1h | Reserved |
23 | RESERVED | R/W | 1h | Reserved |
22 | RESERVED | R/W | 1h | Reserved |
21 | GPIO21 | R/W | 1h | Analog Mode select for this pin Reset type: SYSRSn |
20 | GPIO20 | R/W | 1h | Analog Mode select for this pin Reset type: SYSRSn |
19 | RESERVED | R/W | 1h | Reserved |
18 | RESERVED | R/W | 1h | Reserved |
17 | RESERVED | R/W | 1h | Reserved |
16 | RESERVED | R/W | 1h | Reserved |
15 | RESERVED | R/W | 1h | Reserved |
14 | RESERVED | R/W | 1h | Reserved |
13 | GPIO13 | R/W | 1h | Analog Mode select for this pin Reset type: SYSRSn |
12 | GPIO12 | R/W | 1h | Analog Mode select for this pin Reset type: SYSRSn |
11 | RESERVED | R/W | 1h | Reserved |
10 | RESERVED | R/W | 1h | Reserved |
9 | RESERVED | R/W | 1h | Reserved |
8 | RESERVED | R/W | 1h | Reserved |
7 | RESERVED | R/W | 1h | Reserved |
6 | RESERVED | R/W | 1h | Reserved |
5 | RESERVED | R/W | 1h | Reserved |
4 | RESERVED | R/W | 1h | Reserved |
3 | RESERVED | R/W | 1h | Reserved |
2 | RESERVED | R/W | 1h | Reserved |
1 | RESERVED | R/W | 1h | Reserved |
0 | RESERVED | R/W | 1h | Reserved |
GPAGMUX1 is shown in Figure 8-14 and described in Table 8-22.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | GPIO13 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
25-24 | GPIO12 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
23-22 | GPIO11 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
21-20 | GPIO10 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
19-18 | GPIO9 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
17-16 | GPIO8 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
15-14 | GPIO7 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
13-12 | GPIO6 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
11-10 | GPIO5 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
9-8 | GPIO4 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
7-6 | GPIO3 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | GPIO2 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | GPIO1 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
1-0 | GPIO0 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPAGMUX2 is shown in Figure 8-15 and described in Table 8-23.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | GPIO29 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
25-24 | GPIO28 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | GPIO24 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
15-14 | GPIO23 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
13-12 | GPIO22 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
11-10 | GPIO21 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
9-8 | GPIO20 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
7-6 | GPIO19 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | GPIO18 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | GPIO17 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
1-0 | GPIO16 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPALOCK is shown in Figure 8-16 and described in Table 8-24.
Return to the Summary Table.
GPIO A Lock Configuration Register (GPIO0 to 31)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | GPIO29 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
28 | GPIO28 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | GPIO24 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
23 | GPIO23 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
22 | GPIO22 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
21 | GPIO21 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
20 | GPIO20 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
19 | GPIO19 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
18 | GPIO18 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
17 | GPIO17 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
16 | GPIO16 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | GPIO13 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
12 | GPIO12 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
11 | GPIO11 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
10 | GPIO10 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
9 | GPIO9 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
8 | GPIO8 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
7 | GPIO7 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
6 | GPIO6 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
5 | GPIO5 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
4 | GPIO4 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
3 | GPIO3 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
2 | GPIO2 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
1 | GPIO1 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
0 | GPIO0 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
GPACR is shown in Figure 8-17 and described in Table 8-25.
Return to the Summary Table.
GPIO A Lock Commit Register (GPIO0 to 31)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | GPIO29 | GPIO28 | RESERVED | RESERVED | RESERVED | GPIO24 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/WSonce | 0h | Reserved |
30 | RESERVED | R/WSonce | 0h | Reserved |
29 | GPIO29 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
28 | GPIO28 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
27 | RESERVED | R/WSonce | 0h | Reserved |
26 | RESERVED | R/WSonce | 0h | Reserved |
25 | RESERVED | R/WSonce | 0h | Reserved |
24 | GPIO24 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
23 | GPIO23 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
22 | GPIO22 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
21 | GPIO21 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
20 | GPIO20 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
19 | GPIO19 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
18 | GPIO18 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
17 | GPIO17 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
16 | GPIO16 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
15 | RESERVED | R/WSonce | 0h | Reserved |
14 | RESERVED | R/WSonce | 0h | Reserved |
13 | GPIO13 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
12 | GPIO12 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
11 | GPIO11 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
10 | GPIO10 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
9 | GPIO9 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
8 | GPIO8 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
7 | GPIO7 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
6 | GPIO6 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
5 | GPIO5 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
4 | GPIO4 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
3 | GPIO3 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
2 | GPIO2 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
1 | GPIO1 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
0 | GPIO0 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
GPBCTRL is shown in Figure 8-18 and described in Table 8-26.
Return to the Summary Table.
GPIO B Qualification Sampling Period Control (GPIO32 to 63)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | QUALPRD1 | QUALPRD0 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | 0h | Reserved |
23-16 | RESERVED | R/W | 0h | Reserved |
15-8 | QUALPRD1 | R/W | 0h | Qualification sampling period for GPIO40 to GPIO47: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
7-0 | QUALPRD0 | R/W | 0h | Qualification sampling period for GPIO32 to GPIO39: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
GPBQSEL1 is shown in Figure 8-19 and described in Table 8-27.
Return to the Summary Table.
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 | ||||||||
R/W-0h | R/W-0h | R/W-3h | R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | GPIO41 | R/W | 0h | Select input qualification type for GPIO41: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
17-16 | GPIO40 | R/W | 0h | Select input qualification type for GPIO40: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
15-14 | GPIO39 | R/W | 0h | Select input qualification type for GPIO39: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | GPIO37 | R/W | 3h | Select input qualification type for GPIO37: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | GPIO35 | R/W | 3h | Select input qualification type for GPIO35: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | GPIO33 | R/W | 0h | Select input qualification type for GPIO33: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
1-0 | GPIO32 | R/W | 0h | Select input qualification type for GPIO32: 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
GPBMUX1 is shown in Figure 8-20 and described in Table 8-28.
Return to the Summary Table.
GPIO B Mux 1 Register (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 | ||||||||
R/W-0h | R/W-0h | R/W-3h | R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | GPIO41 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
17-16 | GPIO40 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
15-14 | GPIO39 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | GPIO37 | R/W | 3h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | GPIO35 | R/W | 3h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | GPIO33 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
1-0 | GPIO32 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPBDIR is shown in Figure 8-21 and described in Table 8-29.
Return to the Summary Table.
GPIO B Direction Register (GPIO32 to 63)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | Reserved |
20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | GPIO41 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
8 | GPIO40 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
7 | GPIO39 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
6 | RESERVED | R/W | 0h | Reserved |
5 | GPIO37 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | GPIO35 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
2 | RESERVED | R/W | 0h | Reserved |
1 | GPIO33 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
0 | GPIO32 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
GPBPUD is shown in Figure 8-22 and described in Table 8-30.
Return to the Summary Table.
GPIO B Pull Up Disable Register (GPIO32 to 63)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30 | RESERVED | R/W | 1h | Reserved |
29 | RESERVED | R/W | 1h | Reserved |
28 | RESERVED | R/W | 1h | Reserved |
27 | RESERVED | R/W | 1h | Reserved |
26 | RESERVED | R/W | 1h | Reserved |
25 | RESERVED | R/W | 1h | Reserved |
24 | RESERVED | R/W | 1h | Reserved |
23 | RESERVED | R/W | 1h | Reserved |
22 | RESERVED | R/W | 1h | Reserved |
21 | RESERVED | R/W | 1h | Reserved |
20 | RESERVED | R/W | 1h | Reserved |
19 | RESERVED | R/W | 1h | Reserved |
18 | RESERVED | R/W | 1h | Reserved |
17 | RESERVED | R/W | 1h | Reserved |
16 | RESERVED | R/W | 1h | Reserved |
15 | RESERVED | R/W | 1h | Reserved |
14 | RESERVED | R/W | 1h | Reserved |
13 | RESERVED | R/W | 1h | Reserved |
12 | RESERVED | R/W | 1h | Reserved |
11 | RESERVED | R/W | 1h | Reserved |
10 | RESERVED | R/W | 1h | Reserved |
9 | GPIO41 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
8 | GPIO40 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
7 | GPIO39 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
6 | RESERVED | R/W | 1h | Reserved |
5 | GPIO37 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
4 | RESERVED | R/W | 1h | Reserved |
3 | GPIO35 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
2 | RESERVED | R/W | 1h | Reserved |
1 | GPIO33 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
0 | GPIO32 | R/W | 1h | Pull-Up Disable control for this pin Reset type: SYSRSn |
GPBINV is shown in Figure 8-23 and described in Table 8-31.
Return to the Summary Table.
GPIO B Input Polarity Invert Registers (GPIO32 to 63)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | Reserved |
20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | GPIO41 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
8 | GPIO40 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
7 | GPIO39 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
6 | RESERVED | R/W | 0h | Reserved |
5 | GPIO37 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | GPIO35 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
2 | RESERVED | R/W | 0h | Reserved |
1 | GPIO33 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
0 | GPIO32 | R/W | 0h | Input inversion control for this pin Reset type: SYSRSn |
GPBODR is shown in Figure 8-24 and described in Table 8-32.
Return to the Summary Table.
GPIO B Open Drain Output Register (GPIO32 to GPIO63)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | Reserved |
20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | GPIO41 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
8 | GPIO40 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
7 | GPIO39 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
6 | RESERVED | R/W | 0h | Reserved |
5 | GPIO37 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | GPIO35 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
2 | RESERVED | R/W | 0h | Reserved |
1 | GPIO33 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
0 | GPIO32 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
GPBGMUX1 is shown in Figure 8-25 and described in Table 8-33.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 | ||||||||
R/W-0h | R/W-0h | R/W-3h | R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | ||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | GPIO41 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
17-16 | GPIO40 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
15-14 | GPIO39 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | GPIO37 | R/W | 3h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | GPIO35 | R/W | 3h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | GPIO33 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
1-0 | GPIO32 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPBLOCK is shown in Figure 8-26 and described in Table 8-34.
Return to the Summary Table.
GPIO B Lock Configuration Register (GPIO32 to 63)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | Reserved |
20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | GPIO41 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
8 | GPIO40 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
7 | GPIO39 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
6 | RESERVED | R/W | 0h | Reserved |
5 | GPIO37 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | GPIO35 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
2 | RESERVED | R/W | 0h | Reserved |
1 | GPIO33 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
0 | GPIO32 | R/W | 0h | Configuration Lock bit for this pin Reset type: SYSRSn |
GPBCR is shown in Figure 8-27 and described in Table 8-35.
Return to the Summary Table.
GPIO B Lock Commit Register (GPIO32 to 63)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO41 | GPIO40 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | RESERVED | GPIO37 | RESERVED | GPIO35 | RESERVED | GPIO33 | GPIO32 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/WSonce | 0h | Reserved |
30 | RESERVED | R/WSonce | 0h | Reserved |
29 | RESERVED | R/WSonce | 0h | Reserved |
28 | RESERVED | R/WSonce | 0h | Reserved |
27 | RESERVED | R/WSonce | 0h | Reserved |
26 | RESERVED | R/WSonce | 0h | Reserved |
25 | RESERVED | R/WSonce | 0h | Reserved |
24 | RESERVED | R/WSonce | 0h | Reserved |
23 | RESERVED | R/WSonce | 0h | Reserved |
22 | RESERVED | R/WSonce | 0h | Reserved |
21 | RESERVED | R/WSonce | 0h | Reserved |
20 | RESERVED | R/WSonce | 0h | Reserved |
19 | RESERVED | R/WSonce | 0h | Reserved |
18 | RESERVED | R/WSonce | 0h | Reserved |
17 | RESERVED | R/WSonce | 0h | Reserved |
16 | RESERVED | R/WSonce | 0h | Reserved |
15 | RESERVED | R/WSonce | 0h | Reserved |
14 | RESERVED | R/WSonce | 0h | Reserved |
13 | RESERVED | R/WSonce | 0h | Reserved |
12 | RESERVED | R/WSonce | 0h | Reserved |
11 | RESERVED | R/WSonce | 0h | Reserved |
10 | RESERVED | R/WSonce | 0h | Reserved |
9 | GPIO41 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
8 | GPIO40 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
7 | GPIO39 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
6 | RESERVED | R/WSonce | 0h | Reserved |
5 | GPIO37 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | GPIO35 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | GPIO33 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
0 | GPIO32 | R/WSonce | 0h | Configuration lock commit bit for this pin Reset type: SYSRSn |
GPHCTRL is shown in Figure 8-28 and described in Table 8-36.
Return to the Summary Table.
GPIO H Qualification Sampling Period Control (GPIO224 to 255)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | QUALPRD2 | QUALPRD1 | QUALPRD0 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | 0h | Reserved |
23-16 | QUALPRD2 | R/W | 0h | Qualification sampling period for GPIO240 to GPIO247: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/512 Reset type: SYSRSn |
15-8 | QUALPRD1 | R/W | 0h | Qualification sampling period for GPIO232 to GPIO239: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/511 Reset type: SYSRSn |
7-0 | QUALPRD0 | R/W | 0h | Qualification sampling period for GPIO224 to GPIO231: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 .... 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn |
GPHQSEL1 is shown in Figure 8-29 and described in Table 8-37.
Return to the Summary Table.
GPIO H Qualifier Select 1 Register (GPIO224 to 239)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GPIO239 | GPIO238 | GPIO237 | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO233 | GPIO232 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO231 | GPIO230 | RESERVED | GPIO228 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO227 | GPIO226 | GPIO225 | GPIO224 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | GPIO239 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
29-28 | GPIO238 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
27-26 | GPIO237 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | GPIO233 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
17-16 | GPIO232 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
15-14 | GPIO231 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
13-12 | GPIO230 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | GPIO228 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
7-6 | GPIO227 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
5-4 | GPIO226 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
3-2 | GPIO225 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
1-0 | GPIO224 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
GPHQSEL2 is shown in Figure 8-30 and described in Table 8-38.
Return to the Summary Table.
GPIO H Qualifier Select 2 Register (GPIO240 to 255)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | GPIO245 | GPIO244 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO242 | GPIO241 | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | GPIO245 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
9-8 | GPIO244 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | GPIO242 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
3-2 | GPIO241 | R/W | 0h | 0,0,Sync 0,1,Qualification (3 samples) 1,0,Qualification (6 samples) 1,1,Async (no Sync or Qualification) Reset type: SYSRSn |
1-0 | RESERVED | R/W | 0h | Reserved |
GPHMUX1 is shown in Figure 8-31 and described in Table 8-39.
Return to the Summary Table.
GPIO H Mux 1 Register (GPIO224 to 239)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO230 | RESERVED | GPIO228 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO227 | GPIO226 | RESERVED | GPIO224 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | GPIO230 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | GPIO228 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
7-6 | GPIO227 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | GPIO226 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | GPIO224 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPHMUX2 is shown in Figure 8-32 and described in Table 8-40.
Return to the Summary Table.
GPIO H Mux 2 Register (GPIO240 to 255)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO242 | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | GPIO242 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | RESERVED | R/W | 0h | Reserved |
GPHDIR is shown in Figure 8-33 and described in Table 8-41.
Return to the Summary Table.
GPIO H Direction Register (GPIO224 to 255)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO242 | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | RESERVED | GPIO224 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | Reserved |
20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | GPIO242 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | GPIO230 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
5 | RESERVED | R/W | 0h | Reserved |
4 | GPIO228 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
3 | GPIO227 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
2 | GPIO226 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | GPIO224 | R/W | 0h | Defines direction for this pin in GPIO mode Reset type: SYSRSn |
GPHPUD is shown in Figure 8-34 and described in Table 8-42.
Return to the Summary Table.
GPIO H Pull Up Disable Register (GPIO224 to 255)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO245 | GPIO244 | RESERVED | GPIO242 | GPIO241 | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO239 | GPIO238 | GPIO237 | RESERVED | RESERVED | RESERVED | GPIO233 | GPIO232 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO231 | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | GPIO225 | GPIO224 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30 | RESERVED | R/W | 1h | Reserved |
29 | RESERVED | R/W | 1h | Reserved |
28 | RESERVED | R/W | 1h | Reserved |
27 | RESERVED | R/W | 1h | Reserved |
26 | RESERVED | R/W | 1h | Reserved |
25 | RESERVED | R/W | 1h | Reserved |
24 | RESERVED | R/W | 1h | Reserved |
23 | RESERVED | R/W | 1h | Reserved |
22 | RESERVED | R/W | 1h | Reserved |
21 | GPIO245 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
20 | GPIO244 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
19 | RESERVED | R/W | 1h | Reserved |
18 | GPIO242 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
17 | GPIO241 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
16 | RESERVED | R/W | 1h | Reserved |
15 | GPIO239 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
14 | GPIO238 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
13 | GPIO237 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
12 | RESERVED | R/W | 1h | Reserved |
11 | RESERVED | R/W | 1h | Reserved |
10 | RESERVED | R/W | 1h | Reserved |
9 | GPIO233 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
8 | GPIO232 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
7 | GPIO231 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
6 | GPIO230 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
5 | RESERVED | R/W | 1h | Reserved |
4 | GPIO228 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
3 | GPIO227 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
2 | GPIO226 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
1 | GPIO225 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
0 | GPIO224 | R/W | 1h | 0: Enables the Pull-Up. 1: Disables the Pull-Up. Reading the register returns the current value of the register setting. Note: [1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register. Reset type: SYSRSn |
GPHINV is shown in Figure 8-35 and described in Table 8-43.
Return to the Summary Table.
GPIO H Input Polarity Invert Registers (GPIO224 to 255)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO245 | GPIO244 | RESERVED | GPIO242 | GPIO241 | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO239 | GPIO238 | GPIO237 | RESERVED | RESERVED | RESERVED | GPIO233 | GPIO232 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO231 | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | GPIO225 | GPIO224 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | GPIO245 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
20 | GPIO244 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
19 | RESERVED | R/W | 0h | Reserved |
18 | GPIO242 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
17 | GPIO241 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
16 | RESERVED | R/W | 0h | Reserved |
15 | GPIO239 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
14 | GPIO238 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
13 | GPIO237 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | GPIO233 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
8 | GPIO232 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
7 | GPIO231 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
6 | GPIO230 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
5 | RESERVED | R/W | 0h | Reserved |
4 | GPIO228 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
3 | GPIO227 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
2 | GPIO226 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
1 | GPIO225 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
0 | GPIO224 | R/W | 0h | 0: selects non-inverted GPIO input 1: selects inverted GPIO input Notes: [1] Reading the register returns the current value of the register setting. Reset type: SYSRSn |
GPHODR is shown in Figure 8-36 and described in Table 8-44.
Return to the Summary Table.
GPIO H Open Drain Output Register (GPIO224 to GPIO255)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO242 | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | RESERVED | GPIO224 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | Reserved |
20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | GPIO242 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | GPIO230 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
5 | RESERVED | R/W | 0h | Reserved |
4 | GPIO228 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
3 | GPIO227 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
2 | GPIO226 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | GPIO224 | R/W | 0h | Outpout Open-Drain control for this pin Reset type: SYSRSn |
GPHAMSEL is shown in Figure 8-37 and described in Table 8-45.
Return to the Summary Table.
GPIO H Analog Mode Select register (GPIO224 to GPIO255)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO245 | GPIO244 | RESERVED | GPIO242 | GPIO241 | RESERVED |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO239 | GPIO238 | GPIO237 | RESERVED | RESERVED | RESERVED | GPIO233 | GPIO232 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO231 | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | GPIO225 | GPIO224 |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30 | RESERVED | R/W | 1h | Reserved |
29 | RESERVED | R/W | 1h | Reserved |
28 | RESERVED | R/W | 1h | Reserved |
27 | RESERVED | R/W | 1h | Reserved |
26 | RESERVED | R/W | 1h | Reserved |
25 | RESERVED | R/W | 1h | Reserved |
24 | RESERVED | R/W | 1h | Reserved |
23 | RESERVED | R/W | 1h | Reserved |
22 | RESERVED | R/W | 1h | Reserved |
21 | GPIO245 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
20 | GPIO244 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
19 | RESERVED | R/W | 1h | Reserved |
18 | GPIO242 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
17 | GPIO241 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
16 | RESERVED | R/W | 1h | Reserved |
15 | GPIO239 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
14 | GPIO238 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
13 | GPIO237 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
12 | RESERVED | R/W | 1h | Reserved |
11 | RESERVED | R/W | 1h | Reserved |
10 | RESERVED | R/W | 1h | Reserved |
9 | GPIO233 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
8 | GPIO232 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
7 | GPIO231 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
6 | GPIO230 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
5 | RESERVED | R/W | 1h | Reserved |
4 | GPIO228 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
3 | GPIO227 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
2 | GPIO226 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
1 | GPIO225 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
0 | GPIO224 | R/W | 1h | 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers 1: The analog function of the pin is enabled and the pin is capable of analog functions Reading the register returns the current value of the register setting. Note: [1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect. Reset type: SYSRSn |
GPHGMUX1 is shown in Figure 8-38 and described in Table 8-46.
Return to the Summary Table.
GPIO H Peripheral Group Mux (GPIO224 to 239)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO230 | RESERVED | GPIO228 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO227 | GPIO226 | RESERVED | GPIO224 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | GPIO230 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | GPIO228 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
7-6 | GPIO227 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
5-4 | GPIO226 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | GPIO224 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
GPHGMUX2 is shown in Figure 8-39 and described in Table 8-47.
Return to the Summary Table.
GPIO H Peripheral Group Mux (GPIO240 to 255)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO242 | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | GPIO242 | R/W | 0h | Defines pin-muxing selection for GPIO Reset type: SYSRSn |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | RESERVED | R/W | 0h | Reserved |
GPHLOCK is shown in Figure 8-40 and described in Table 8-48.
Return to the Summary Table.
GPIO H Lock Configuration Register (GPIO224 to 255)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO245 | GPIO244 | RESERVED | GPIO242 | GPIO241 | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO239 | GPIO238 | GPIO237 | RESERVED | RESERVED | RESERVED | GPIO233 | GPIO232 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO231 | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | GPIO225 | GPIO224 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | Reserved |
30 | RESERVED | R/W | 0h | Reserved |
29 | RESERVED | R/W | 0h | Reserved |
28 | RESERVED | R/W | 0h | Reserved |
27 | RESERVED | R/W | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | GPIO245 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
20 | GPIO244 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
19 | RESERVED | R/W | 0h | Reserved |
18 | GPIO242 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
17 | GPIO241 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
16 | RESERVED | R/W | 0h | Reserved |
15 | GPIO239 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
14 | GPIO238 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
13 | GPIO237 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | GPIO233 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
8 | GPIO232 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
7 | GPIO231 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
6 | GPIO230 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
5 | RESERVED | R/W | 0h | Reserved |
4 | GPIO228 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
3 | GPIO227 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
2 | GPIO226 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
1 | GPIO225 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
0 | GPIO224 | R/W | 0h | 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin 0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed Reset type: SYSRSn |
GPHCR is shown in Figure 8-41 and described in Table 8-49.
Return to the Summary Table.
GPIO H Lock Commit Register (GPIO224 to 255)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | GPIO245 | GPIO244 | RESERVED | GPIO242 | GPIO241 | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO239 | GPIO238 | GPIO237 | RESERVED | RESERVED | RESERVED | GPIO233 | GPIO232 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO231 | GPIO230 | RESERVED | GPIO228 | GPIO227 | GPIO226 | GPIO225 | GPIO224 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/WSonce | 0h | Reserved |
30 | RESERVED | R/WSonce | 0h | Reserved |
29 | RESERVED | R/WSonce | 0h | Reserved |
28 | RESERVED | R/WSonce | 0h | Reserved |
27 | RESERVED | R/WSonce | 0h | Reserved |
26 | RESERVED | R/WSonce | 0h | Reserved |
25 | RESERVED | R/WSonce | 0h | Reserved |
24 | RESERVED | R/WSonce | 0h | Reserved |
23 | RESERVED | R/WSonce | 0h | Reserved |
22 | RESERVED | R/WSonce | 0h | Reserved |
21 | GPIO245 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
20 | GPIO244 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
19 | RESERVED | R/WSonce | 0h | Reserved |
18 | GPIO242 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
17 | GPIO241 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
16 | RESERVED | R/WSonce | 0h | Reserved |
15 | GPIO239 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
14 | GPIO238 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
13 | GPIO237 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
12 | RESERVED | R/WSonce | 0h | Reserved |
11 | RESERVED | R/WSonce | 0h | Reserved |
10 | RESERVED | R/WSonce | 0h | Reserved |
9 | GPIO233 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
8 | GPIO232 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
7 | GPIO231 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
6 | GPIO230 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
5 | RESERVED | R/WSonce | 0h | Reserved |
4 | GPIO228 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
3 | GPIO227 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
2 | GPIO226 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
1 | GPIO225 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |
0 | GPIO224 | R/WSonce | 0h | 1: Locks changes to the bit in GPyLOCK register which controls the same pin 0: Bit in the GPyLOCK register which controls the same pin can be changed Reset type: SYSRSn |