SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

2.4.2 Protected Call Stack

The Protected Call Stack is a dedicated hardware stack used to make protected function call and return. This stack is directly controlled by CPU and is inaccessible to user code. The basic protection concept of the C29x CPU is based on LINKs, STACKs, and ZONEs. The protected function call and return is the method used to make a function call by the current executing code to another function residing in a different STACK. The C29x security architecture allows definition of legal callable function labels using the instructions ENTRY1.PROT and ENTRY2.PROT. This makes sure that code from another STACK can only make function calls or branches to labels with the instruction packet “ENTRY1.PROT || ENTRY2.PROT” present. This prevents malicious code from randomly entering into code regions without permission. Nesting of protected calls is allowed up to the number of levels supported by the protected call stack. Table 2-8 shows the rules of code execution across stack.

Protected call Stack Pointer (PSP) register: The PSP register keeps track of the utilization of protected call stack and shows the current value of protected call stack pointer. This register is automatically incremented and decremented by HW on a protected call (CALL.PROT) and protected return (RET. PROT) respectively.

Warning level for Protected call Stack Pointer (WARNPSP) register: This WARNPSP is a user configurable register which allows early warning of protected stack overflow detection. When PSP register >= WARNPSP register, error signal is generated to ESM.

Maximum Protected call Stack Pointer (MAXPSP) register: The MAXPSP register is not user configurable register. When PSP register = MAXPSP register, CPU enters fault state as protected call stack is full.

Table 2-8 Rules of Code Execution Across STACKs
Program Flow Operation Comments and CPU Action
Linear code execution within the same LINK Allowed without any restriction
Branches, calls and returns within the same LINK
Branches, calls and returns across different LINKs, but within the same STACK
Protected function return (RET.PROT) where the return address is on a different STACK compared to the current STACK
Protected function calls (CALL.PROT @label/Ax) where source and destination are on same STACK
Protected function return (RET.PROT) where the return address is on a same STACK
Linear code execution crossing LINK, but within the same STACK Not allowed, CPU enters FAULT state.
Branches where source and destination are on different STACKs
Function calls (CALL{D} @label/Ax) where source and destination are on different STACKs
Execution of a function return instruction (RET{D} /RET{D} <addr1>) where the return address is on a different STACK compared to the current STACK
Realtime Interrupt (RTINT) and NMI This is handled in the hardware and does not need any consideration in the user code. The Interrupt service routine can reside in the same or a different LINK/STACK/ZONE.
Interrupts (INT) ISR must be on the same stack. If not, CPU enters FAULT state.